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參數(shù)資料
| 型號(hào)： | HY5S6B6DSF-BE |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4Banks x1M x 16bits Synchronous DRAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 9 ns, PBGA54 |
| 封裝： | 0.80 MM PITCH, FBGA-54 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大小： | 368K |
| 代理商： | HY5S6B6DSF-BE |
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Rev 0.3 / July 2004
25
HY5S6B6D(L/S)F(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole
memory array of the devices.
Data will not be retained once the device enters Deep Power Down Mode.
Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
the clock, while CKE is low. The following diagram illustrates deep power down mode entry.
Current State
Idle
Deep Power Down
Command
CKE
n-1
H
L
CKE
n
L
H
CS
L
X
RAS
H
X
CAS
H
X
WE
L
X
Deep Power Down Entry
Deep Power Down Exit
CLK
CKE
CS
RAS
CAS
WE
t
RP
Precharge
if needed
Deep Power Down Entry
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5S6B6DSFP-BE | 4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DSFP-SE | 4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DSF-SE | 4Banks x1M x 16bits Synchronous DRAM |
| HY62256A | 32Kx8bit CMOS SRAM |
| HY62256ALLJ | 32Kx8bit CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5S6B6DSFP-BE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DSFP-SE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DSF-SE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x1M x 16bits Synchronous DRAM |
| HY5S7B2ALFP-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M (16Mx32bit) Mobile SDRAM |
| HY5S7B2ALFP-6E | 制造商:SK Hynix Inc 功能描述: |
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