參數(shù)資料
型號(hào): HY5S6B6DLF-SE
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 4Banks x1M x 16bits Synchronous DRAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝: 0.80 MM PITCH, FBGA-54
文件頁(yè)數(shù): 24/27頁(yè)
文件大?。?/td> 368K
代理商: HY5S6B6DLF-SE
Rev 0.3 / July 2004
24
HY5S6B6D(L/S)F(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note : 1. A new command can be given t
RC
after self refresh exit.
Parameter
Symbol
S
B
Unit
Note
Min
Max
Min
Max
RAS Cycle Time
t
RC
90
-
90
-
ns
RAS to CAS Delay
t
RCD
28.5
-
30
-
ns
RAS Active Time
t
RAS
60
100K
60
100K
ns
RAS Precharge Time
t
RP
28.5
-
30
-
ns
RAS to RAS Bank Active Delay
t
RRD
19
-
30
-
ns
CAS to CAS Delay
t
CCD
1
-
1
-
CLK
Write Command to Data-In Delay
t
WTL
0
-
0
-
CLK
Data-in to Precharge Command
t
DPL
2
-
2
-
CLK
Data-In to Active Command
t
DAL
t
DPL
+t
RP
DQM to Data-Out Hi-Z
t
DQZ
2
-
2
-
CLK
DQM to Data-In Mask
t
DQM
0
-
0
-
CLK
MRS to New Command
t
MRD
2
-
2
-
CLK
Precharge to Data Output
High-Z
CAS Latency=3
t
PROZ3
3
-
3
-
CLK
CAS Latency=2
t
PROZ2
2
2
CLK
Power Down Exit Time
t
DPE
1
-
1
-
CLK
Auto Refresh Cycle Time
t
ARFC
90
105
ns
Self Refresh Exit Time
t
SRE
1
-
1
-
CLK
1
Refresh Time
t
REF
-
64
-
64
ms
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