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參數(shù)資料
| 型號(hào)： | HY5PS121623F |
| 英文描述： | 32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 32Mx16 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁(yè)數(shù)： | 57/66頁(yè) |
| 文件大?。?/td> | 862K |
| 代理商： | HY5PS121623F |
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Rev. 0.52/Nov. 02 57
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Symbol
Test Condition
533
4/4/4
400
3/3/3
4/4/4Unit Note
Operating Current
IDD0
One ban; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
TBD
TBD
TBD
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst Length=4; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle
TBD
TBD
TBD
mA
Precharge Power Down
Standby Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
TBD
TBD
TBD
mA
Idle Standby Current
I
DD2F
CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and DM
TBD
TBD
TBD
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
TBD
TBD
TBD
mA
Active Standby Current
I
DD3N
CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
TBD
TBD
TBD
mA
Operating Current
I
DD4R
Burst=4; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
TBD
TBD
TBD
mA
Operating Current
I
DD4W
Burst=4; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
TBD
TBD
TBD
Auto Refresh Current
I
DD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR II at 133Mhz; distributed
refresh
TBD
TBD
TBD
Self Refresh Current
I
DD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
TBD
TBD
TBD
mA
Low Power
TBD
TBD
TBD
mA
Operating Current -
Four Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
TBD
TBD
TBD
mA
This Page will be changed by the standardization result of Jedec Committee.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HY5PS121623LF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32Mx16|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| HY5PS12421AF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM |
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