參數(shù)資料
型號： HY5DU56422DLTP
廠商： Hynix Semiconductor Inc.
英文描述： 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
中文描述： 256M DDR內(nèi)存（268435456位CMOS雙數(shù)據(jù)速率（DDR）同步DRAM）
文件頁數(shù)： 13/37頁
文件大小： 414K
代理商： HY5DU56422DLTP
Rev. 0.1 /May 2004 13
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
OPERATION COMMAND TRUTH TABLE-IV
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Current
State
/CS
/RAS
/CAS
/WE
Address
Command
Action
WRITE
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
11
L
L
H
H
BA, RA
ACT
ILLEGAL
11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL
11
L
L
L
H
X
AREF/SREF
ILLEGAL
11
L
L
L
L
OPCODE
MRS
ILLEGAL
11
MODE
REGISTER
ACCESSING
H
X
X
X
X
DSEL
NOP - Enter IDLE after tMRD
L
H
H
H
X
NOP
NOP - Enter IDLE after tMRD
L
H
H
L
X
BST
ILLEGAL
11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL
11
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
11
L
L
H
H
BA, RA
ACT
ILLEGAL
11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL
11
L
L
L
H
X
AREF/SREF
ILLEGAL
11
L
L
L
L
OPCODE
MRS
ILLEGAL
11
相關(guān)PDF資料
PDF描述
HY5DU56422DLTP-H 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-J 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-K 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-L 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-M 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU56422DLTP-H 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-J 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-K 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-L 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
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