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參數資料
| 型號： | HY5DS113222FM-4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 512M(16Mx32) GDDR SDRAM |
| 中文描述： | 16M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, MO-205DAE, FBGA-144 |
| 文件頁數： | 7/30頁 |
| 文件大?。?/td> | 431K |
| 代理商： | HY5DS113222FM-4 |
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Rev. 0.1 / Oct. 2004
7
HY5DS113222FM(P)
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS0/
CS1
RAS
CAS
WE
ADDR
A8/
AP
BA
Note
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2,6
Mode Register Set
H
X
L
L
L
L
OP code
1,2,6
Device Deselect
H
X
H
X
X
X
X
1
No Operation
L
H
H
H
Bank Active
H
X
L
L
H
H
RA
V
1
Read
H
X
L
H
L
H
CA
L
V
1,7
Read with Autoprecharge
H
1,3,7
Write
H
X
L
H
L
L
CA
L
V
1,7
Write with Autoprecharge
H
1,4,7
Precharge All Banks
H
X
L
L
H
L
X
H
X
1,5
Precharge selected Bank
L
V
1
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Self Refresh
Entry
H
L
L
L
L
H
X
1,6
Exit
L
H
H
X
X
X
1,6
L
H
H
H
Precharge Power
Down Mode
Entry
H
L
H
X
X
X
X
1,6
L
H
H
H
1,6
Exit
L
H
H
X
X
X
1,6
L
H
H
H
1,6
Active Power
Down Mode
Entry
H
L
H
X
X
X
X
1,6
L
V
V
V
1,6
Exit
L
H
X
1,6
Note :
1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
6. Both of CS0 & CS1 should be enabled simultaneously.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
相關PDF資料 |
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| HY5DS113222FMP-28 | 512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-33 | 512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-36 | 512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-4 | 512M(16Mx32) GDDR SDRAM |
| HY5DS283222BF | 128M(4Mx32) GDDR SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY5DS113222FMP-28 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DS283222BF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
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