參數(shù)資料
型號: HY57V161610ET-55
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 2 Banks x 512K x 16 Bit Synchronous DRAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO50
封裝: 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
文件頁數(shù): 8/13頁
文件大?。?/td> 181K
代理商: HY57V161610ET-55
HY57V161610E
Rev. 0.2 / Aug. 2003
8
AC CHARACTERISTICS
(TA=0
°
C
to 70
°
C
, V
DD
=3.0V to
3.6V, V
SS
=0V
Note1,2
)
- continued -
Note :
1.V
DD
(min) is 3.15V when HY57V161610ET-7 operates at CAS latency=2 and tCK2=8.9ns.
2.V
DD
(min) of HY57V161610ET-5/55 is 3.15V
3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610ET-6 and HY57V161610ET-7.
4.Assume tR / tF (input rise and fall time ) is 1ns.
Parameter
Symbol
-8
-10
-15
Unit
Note
Min
Max
Min
Max
Min
Max
System clock cycle
time
CL=3
tCK3
8
-
10
-
15
-
ns
CL=2
tCK2
12
-
12
-
15
-
3
CL=1
tCK1
-
-
-
-
15
-
Clock high pulse width
tCHW
3
-
3
-
3
-
ns
4
Clock low pulse width
tCLW
3
-
3
-
3
-
ns
4
Access time from
clock
CL=3
tAC3
-
6
-
7
-
7
ns
CL=2
tAC2
-
6
-
7
-
7
3
CL=1
tAC1
-
-
-
-
-
14
Data-out hold time
tOH
2.5
-
2.5
-
2.5
-
ns
Data-Input setup time
tDS
2
-
2.5
-
2.5
-
ns
4
Data-Input hold time
tDH
1
-
1
-
1
-
ns
4
Address setup time
tAS
2
-
2.5
-
2.5
-
ns
4
Address hold time
tAH
1
-
1
-
1
-
ns
4
CKE setup time
tCKS
2
-
2.5
-
2.5
-
ns
4
CKE hold time
tCKH
1
-
1
-
1
-
ns
4
Command setup time
tCS
2
-
2.5
-
2.5
-
ns
4
Command hold time
tCH
1
-
1
-
1
-
ns
4
CLK to data output in low Z-time
tOLZ
2
-
2
-
2
-
ns
CLK to data output in high Z-time
tOHZ
2
8
3
10
3
15
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY57V161610ET-55I 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610ET-5I 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610ET-6 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610ET-6I 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2 Banks x 512K x 16 Bit Synchronous DRAM
HY57V161610ET-7 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2 Banks x 512K x 16 Bit Synchronous DRAM