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參數(shù)資料
| 型號： | HV506X |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 275V 40-Channel Row Driver with SCR Outputs |
| 中文描述： | EL DISPLAY DRIVER, UUC57 |
| 封裝： | 3.124 X 3.886 MM, DIE-57 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 464K |
| 代理商： | HV506X |
3
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
t
W (H/L)
t
SUD
t
HD
t
SUC
t
SUE
t
HC
t
HE
t
DHL*
t
DLH*
t
OFF(SCR)
Clock frequency
3
MHz
Pulse width - clock high or low
150
ns
Data set-up time before clock rises
50
ns
Data hold time after clock rises
50
ns
HV
OUT
delay from clock rises (Hi-Z to H or L)
HV
OUT
delay from Output Enable rises
HV
OUT
delay from clock rises (H or L to Hi-Z)
HV
OUT
delay from Output Enable rises
Delay time clock to data output falls
1
μ
s
C
L
= 10nF
C
L
= 10nF
C
L
= 10nF
C
L
= 10nF
C
L
= 15pF
C
L
= 15pF
Time after I
OUT
≤
2mA,
C
L
= 10nF
Time after I
OUT
≤
2mA,
C
L
= 10nF
600
ns
2
μ
s
600
ns
250
ns
Delay time clock to data output rises
250
ns
Turn off time of output SCR
4
μ
s
t
OFF(D)
Turn off time of output diode
2
μ
s
t
POW
t
OEW
SR
POL pulse width
3
μ
s
Output Enable pulse width
3
μ
s
Slew rate of HV
OUT
200
V/
μ
s
AC Characteristics
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to t
WH
. Therefore the delay is measured from the trailing edge of the clock.
HV506
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