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參數(shù)資料
| 型號： | HTG2190 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit 1024 Pixel LCD Microcontroller |
| 中文描述： | 8位單片機1024像素LCD |
| 文件頁數(shù)： | 36/64頁 |
| 文件大?。?/td> | 417K |
| 代理商： | HTG2190 |
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HTG2190
Rev. 1.00
36
June 29, 2001
On the above table, we can easily see that the
sampling rate is dependent on the system clock.
If start bit is set to 1 , the PWM2 and PWM1
will output a GND level voltage.
Label
Bits
Function
PWM dis/EN
0
Enable/disable
PWM output
0: enable, 1: disable
BZ/SP
1
Output driver select
1:buzzer ; 0:speaker
6/7 Bits
2
PWM counter bit select
1:7 bits ; 0:6 bits
P0~P2
3~5
3 bits preload counter
Bit543: 000B~111B (0~7)
Bit3: LSB
D0, D1
6, 7 PWMI
PWMC register
D1
D0
PWM Interrupt
0
0
1
0
1
2
1
0
4
1
1
8
The ratio of latch to interrupt
Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
7-bit
D7
D6
D5
D4
D3
D2
D1
D0
6-bit
D7
D6
D5
D4
D3
D2
D1
X
PWM data buffer
Note: "X" stands for don t care
bit7: Sign bit
Serial I/O interface function
The serial interface of the HTG2190 has two
types of operation mode: master mode and
slave mode.
In the master mode, it uses an internal clock as
synchronous clock. In the slave mode, the syn-
chronous output from the external (master
side) serial device is input.
The master mode and slave mode are selected
through registers SERC.2 and SERC.3; when
the master mode is selected, a synchronous
clock may be selected from among 2 types as
shown in table.
SERC.3 SERC.2
Mode
Synchronous
Clock
1
1
Slave mode External clock
1
0
Master
mode
SCLKS
0
1
Master
mode
SCLKX
0
0
No used
SOUT is latch data at H to L by fixed mode
SERC
SCLKX
SCLKS
b6
b5
b4
0
0
0
16K
f
SYS
/4
0
0
1
8K
f
SYS
/8
0
1
0
4K
f
SYS
/16
0
1
1
2K
f
SYS
/32
1
0
0
1K
f
SYS
/64
1
0
1
512
f
SYS
/128
1
1
0
256
f
SYS
/256
1
1
1
128
f
SYS
/512
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