HT82K94E/HT82K94A
Rev. 1.00
21
November 22, 2005
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H
check not ready (01H)
01H
delay 2 s, check 41H
read* from FIFO0 register and
03H
02H
Write FIFO1 sequence
0AH
check not ready (0BH)
0BH
delay 2 s, check 4BH
09H
write* to FIFO1 register and
08H
Check whether FIFO0 can be read or not
00H
01H
delay 2 s, check 41H (ready) or 01H (not ready)
00H
Check whether FIFO1 can be written or not
0AH
0BH
delay2 s,check4BH(ready)or0BH(notready)
0AH
Read 0-sized packet sequence form FIFO0
00H
01H
delay 2 s, check 81H
read once (01H)
03H
02H
Write 0-sized packet sequence to FIFO1
0AH
0BH
delay 2 s, check 0BH
0FH
0DH
08H
Note:
*: There are 2 s existing between 2 reading action or between 2 writing action
USB/PS2 Status and Control Register
The register is used to indicate there are USB suspend, USB resume and USB reset signal in USB bus. Also user can
output a high pulse in RMWK bit to wake-up the PC for USB remote function.
Bit No.
Label
R/W
Function
0
SUSP
R
Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indi-
cates the USB bus enters suspend mode. The USB interrupt is also triggered on any
changes of this bit.
1
RMWK
W
USB remote wake-up command. It is set by MCU to force the USB host leaving the
suspend mode. When this bit is set to 1 , 2 s delay for clearing this bit to 0 is
needed to insure the RMWK command is accepted by SIE.
2
URST
R/W
USB reset indication. This bit is set/cleared by USB SIE. This bit is used to detect
which bus (PS2 or USB) is attached. When the URST is set to 1 , this indicates that
a USB reset has occurred (the attached bus is USB) and a USB interrupt will be ini-
tialized.
3
RESUME
R
USB resume indication. When the USB leaves the suspend mode, this bit is set to
1 (set by SIE). This bit will appear 20ms waiting for the MCU to detect. When the
RESUME is set by the SIE, an interrupt will be generated to wake-up the MCU. In or-
der to detect the suspend state, the MCU should set the USBCKEN and clear
SUSP2 (in SCC register) to enable the SIE detecting function. The RESUME will be
cleared while the SUSP is going 0 . When the MCU is detecting the SUSP, the RE-
SUME (wakes-up the MCU ) should be remembered and taken into consideration.
4
PS2DAI
R
Read only, USBD-/DATA input
5
PS2CKI
R
Read only, USBD+/CLK input
6
PS2DAO
W
Data for driving the USBD-/DATA pin (Default= 1 )
7
PS2CKO
W
Data for driving the USBD+/CLK pin (Default= 1 )
USC (1CH) Register