HT82K94E/HT82K94A
Rev. 1.00
15
November 22, 2005
Bit No.
Label
Function
0~2, 5
Unused bit, read as 0
3
TE
To define the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
4
TON
To enable/disable timer 1 counting (0=disabled; 1=enabled)
6
7
TM0
TM1
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
, !
( +
" $
!
"
(
,
)
(
(
,
" (
!
)
(
( 1
!
,
"
% , B
(
%
'
) *
Timer/Event Counter 0
, !
( +
" $
!
"
(
,
2 ( 1
!
)
(
,
" (
!
( 1
!
,
"
% , B
(
%
'
) *
2 ( 1
!
)
(
9
> )
# :
#
B ( 1
% %
1
Timer/Event Counter 1
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 0. The internal clock
source is coming from f
SYS
/4.
The external clock input allows the user to count exter-
nal events, measure time intervals or pulse widths.
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 1. The internal clock
source is coming from f
SYS
/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
There are 2 registers related to the Timer/Event Counter
0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical regis-
ters are mapped to TMR0 location; writing TMR0 makes
the starting value be placed in the Timer/Event Counter
0 preload register and reading TMR0 gets the contents
of the Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which defines some
options.
There are 3 registers related to Timer/Event Counter 1;
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H op-
erations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting en-
able or disable and active edge.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external