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參數(shù)資料
| 型號： | HT48R32(20DIP-F0) |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 259K |
| 代理商： | HT48R32(20DIP-F0) |
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HT48R50A-1/HT48C50-1
Rev. 1.00
17
January 2, 2003
Timer/Event Counter 0/1 (reading TMR0/TMR1) is read,
the clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into
consideration by the programmer.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 0. The definitions are as shown.
The overflow signal of Timer/Event Counter 0 can be
used to generate PFD signals for buzzer driving.
Input/output ports
There are 35 bidirectional input/output lines in the
microcontroller, labeled from PA to PD and PG, which are
mapped to the data memory of [12H], [14H], [16H], [18H]
and [1EH] respectively. All of these I/O ports can be used
for input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready at
the T2 rising edge of instruction MOV A,[m] (m=12H,
14H, 16H, 18H or 1EH). For output operation, all the data
is latched and remains unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PGC) to control the input/output configura-
tion. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically (i.e. on-the-fly) under
software control. To function as an input, the corre-
sponding latch of the control register must write 1 . The
input source also depends on the control register. If the
control register bit is 1 , the input will read the pad
state. If the control register bit is 0 , the contents of the
latches will move to the internal bus. The latter is possi-
ble in the read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H, 19H and 1FH.
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H, 18H or 1EH) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the de-
vice. The highest 5-bit of port G are not physically imple-
mented;onreadingthema 0 isreturnedwhereaswriting
then results in no-operation. See Application note.
There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is se-
lected, the I/O line have pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PB0/PB1 will be the PFD signal
generated by Timer/Event Counter 0 overflow signal.
The input mode always remain in its original functions.
Once the BZ/BZ option is selected, the buzzer output
signals are controlled by the PB0 data register only.
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Input/output ports
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