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參數(shù)資料
| 型號： | HSP43168JC-33Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIR FILTER DUAL 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | FIR |
| 濾波器數(shù)： | 2 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
4
FN2808.12
July 27, 2009
Pin Description
SYMBOL
TYPE
DESCRIPTION
VCC
VCC: +5V power supply pin
GND
Ground
CIN0-9
I
Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB
A0-8
I
Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the
LSB
WR
I
Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of WR
CSEL0-4
I
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input
is registered and CSEL0 is the LSB.
INA0-9
I
Input to FIR A. INA0 is the LSB
INB0-9
I/O
Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the
output bus, and INB9 is the MSB of these bits.
OUT9-27
O
19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27
is the MSB.
SHFTEN
I
Shift Enable. This active low input enables clocking of data into the part and shifting of data through the Decimation
Registers.
FWRD
FWD
I
Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through
the “a” input. When high, the “a” inputs to the ALUs are zeroed.
RVRS
I
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through
the “b” input. When high, the “b” inputs to the ALUs are zeroed.
TXFR
I
Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with
the LIFO being written from the forward decimation path (see Figure 1).
MUX0-1
I
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various
configurations.
CLK
I
Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables
(OEL, OEH) are registered by the rising edge of CLK.
OEL
I
Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low.
OEH
I
Output Enable High. This three-state control enables OUT9-27 when OEH is low.
ACCEN
I
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input
latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the
Accumulator.
NC
No connect
HSP43168
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| HSP43168JC-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC, 40MHZ, COMM - Bulk |
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| HSP43168JC-45S5001 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43168JI-40 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 84 PLCC 40MHZ,INDUSTRIAL TEMP - Bulk |
| HSP43168VC-33 | 制造商:Rochester Electronics LLC 功能描述:DUAL DIGITAL FILTER 100 PQFP, 33MHZ, COMM - Bulk 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
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