參數(shù)資料
型號(hào)： HPC3130PBMQUADFLAT
廠商： Texas Instruments, Inc.
英文描述： PCI HOT PLUG CONTROLLER
中文描述： 的PCI熱插拔控制器
文件頁(yè)數(shù)： 31/40頁(yè)
文件大?。?/td> 555K
代理商： HPC3130PBMQUADFLAT
HPC3130
PCI HOT PLUG CONTROLLER
SCPS029B – DECEMBER1998
31
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt event enable register
Bit
7
6
5
4
3
2
1
0
Name
Interrupt event enable register
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Description:
Interrupt event enable
Read-only, Read/Write
07h (slot 0), 0Fh (slot 1), 17h (slot 2), 1Fh (slot 3)
00h
This register is used to enable interrupts, signaled through the open-drain INTR, after
detecting various events. Event status is reported through the interrupt event status
register.
Table 13. Interrupt Event Enable Register
BIT
TYPE
NAME
FUNCTION
7
R
RSVD
Reserved. This bit returns 0 when read.
6
R/W
BUS_E
PCI bus CBT switch event enable. When this bit is set, an INTR is signaled when the BUSON output is
driven low. The BUS event is intended for use with the idling protocol.
5
R/W
PWRGOOD_E
Power good event enable. When this bit is set, an INTR is signaled when the PWRGOOD input changes
state.
4
R/W
PWRFAULT_E
Power fault event enable. When this bit is set, an INTR is signaled when PWRFAULT input is asserted.
3
R/W
DETECT1_E
Mechanical detect 1 event enable. Enables INTR events on DETECT1 input state changes.
2
R/W
DETECT0_E
Mechanical detect 0 event enable. Enables INTR events on DETECT0 input state changes.
1
R/W
PRSNT2_E
Card present 2 event enable. Enables INTR events on PRSNT2 input state changes.
0
R/W
PRSNT1_E
Card present 1 event enable. Enables INTR events on PRSNT1 input state changes.
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