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參數(shù)資料
| 型號： | HPC3130PBMQUADFLAT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PCI HOT PLUG CONTROLLER |
| 中文描述： | 的PCI熱插拔控制器 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 555K |
| 代理商： | HPC3130PBMQUADFLAT |
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HPC3130
PCI HOT PLUG CONTROLLER
SCPS029B – DECEMBER1998
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
If automatic sequencing mode 1 is selected, then the BUS_CTL bit controls the sequencing by using idling
protocol. When this bit is set to zero, the switch–timing block will arbitrate for the PCI Bus by asserting IDLEREQ.
Subsequently, IDLEGNT is asserted and the HPC3130 waits for bus idle condition. When FRAME and IRDY
are deasserted, the CBT switches are enabled. Following this, the SLOTRST, SLOTREQ64 and REQ64ON are
deasserted. Figure 7 depicts the sequencing of events when automatic sequencing mode 1 is enabled.
PCI_CLK
PWRON/OFF
PWRGOOD
SLOTRST
CLKON
REQ64ON
SLOTREQ64
BUS_CTL
IDLEREQ
IDLEGNT
FRAME
IRDY
BUSON
Figure 7. Automatic Connection Sequencing Mode 1
If automatic sequencing mode 2 is selected, then the BUS_CTL bit controls the sequencing by using idling
protocol. When this bit is set to zero, the switch timing block arbitrates for the PCI bus by asserting IDLEREQ.
Subsequently, IDLEGNT is asserted and the HPC3130 waits for the bus idle condition. When FRAME and IRDY
are deasserted, the SLOTRST is deasserted. Following this, the SLOTREQ64 and REQ64ON are deasserted
and the CBT switches are enabled. Figure 8 depicts the sequencing of events when automatic sequencing
mode 2 is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
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| HPC3130PGE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
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| HPC36003 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microControllers |
| HPC36003E30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| HPC36003L30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
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