參數(shù)資料
型號： HPC3130PBKLOW-PROFILEQUAD
廠商： Texas Instruments, Inc.
英文描述： PCI HOT PLUG CONTROLLER
中文描述： 的PCI熱插拔控制器
文件頁數(shù)： 13/40頁
文件大?。?/td> 555K
代理商： HPC3130PBKLOW-PROFILEQUAD
HPC3130
PCI HOT PLUG CONTROLLER
SCPS029B – DECEMBER1998
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
system interface
TERMINAL
NO.
120
NAME
NO.
128
NO.
144
I/O
FUNCTION
FRAME
20
21
23
I
Frame. This input and the IRDY input indicate that the PCI bus is idle. When the HPC3130
senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot can be connected to the PCI
bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented.
IDLEGNT
19
20
22
I
Idle grant. This input indicates when the PCI bus is idled by the HOST-PCI bridge after a
request is made by IDLEREQ. The protocol is identical to PCI request/grant. This input must be
wired to a valid logic level if the bus idling procedure is not implemented.
IDLEREQ
18
19
21
O
Idle request. This output is driven to request the HOST-PCI bridge to idle the PCI bus before
connecting a hot-plug slot. The protocol is identical to PCI request/grant. A pullup resistor must
be implemented on this terminal if the bus idling procedure is not implemented.
INTR
24
25
27
O
System interrupt. This output provides a system interrupt. The HPC3130 can be programmed
to assert this interrupt under various conditions, which may be serviced by the hot-plug service.
Furthermore, the event status/enable state is compliant with the ACPI Specificationand, as a
result, supports ACPI control methods for switching the HPC3130.
INTR
23
24
26
O
System interrupt. This open drain output provides a system interrupt. The HPC3130 can be
programmed to assert this interrupt under various conditions, which may be serviced by the
hot-plug. Furthermore, the event status/enable state is compliant with the ACPI Specification
and, as a result, supports ACPI control methods for switching the HPC3130.
IRDY
21
22
24
I
Initiator ready. This and the FRAME input indicate that the PCI bus is idle. When the HPC3130
senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot may be connected to the PCI
bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented.
PCLK
16
17
19
I
PCI clock input. These terminals provide the PCI clock to the HPC3130, which uses it only for
activity indicator timing, IDLEREQ/IDLEGNT protocol, and connection sequencing.
PRST
14
15
17
I
PCI reset. This signal provides the PCI reset to the HPC3130. After a PCI reset, the HPC3130
resides in a state where all slots are enabled, as in a non-hot-plug system. The HPC3130
passes PCI resets from the host to all hot-plug slots.
SGNT
13
14
16
O
Secondary grant. This output provides a scheme to cascade a secondary HPC3130 device in
order to provide more than four slots. The SGNT output from the primary HPC3130 is input to
the IDLEGNT terminal for the secondary HPC3130. After the secondary HPC3130 requests
the primary HPC3130 to idle the bus, the primary HPC3130 arbitrates for the bus using
IDLEREQ. Once IDLEGNT is asserted, the primary HPC3130 asserts its SGNT output. This
indicates to the secondary HPC3130 device that it can connect to the bus.
SMODE
27
28
30
I
Serial bus mode. When this input is asserted high, the internal HPC3130 registers are
accessible through serial bus interface; otherwise, they are accessed through the generic
parallel bus interface. This input selects the control bus interface.
SREQ
12
13
15
I
Secondary request. This input provides a scheme to cascade a second HPC3130 device in
order to provide more than four slots. The IDLEREQ from the second HPC3130 device is input
to the SREQ terminal of the primary HPC3130. If the second HPC3130 device arbitrates for the
bus by asserting its IDLEREQ output, this scheme causes the primary HPC3130 to assert its
IDLEREQ. If cascading is not used, this input is pulled high.
SYSM66EN
25
26
28
I/O
PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of the
hot-plug slots, and must be tied to the system PCI bus M66EN signal. The output from this
terminal only changes state after a PCI reset and is only required in a 66-MHz system.
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