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參數(shù)資料
| 型號： | HPA00036DTR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Single Ended Active Clamp/Reset PWM |
| 中文描述： | 單端有源鉗位/復位脈寬調(diào)制 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 568K |
| 代理商： | HPA00036DTR |
2
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
I
VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
LINE, RAMP . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to VDD + 1V
I
LINE
, I
RAMP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3V
I
DELAY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
I
OUT1
(tpw < 1 s and Duty Cycle < 10%). . . . . . . 0.6A to 1.2A
I
OUT2
(tpw < 1 s and Duty Cycle < 10%). . . . . . . 0.4A to 0.4A
I
CLK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA to 100mA
OSC1, OSC2, SS, SHTDWN, EAIN . . . . . 0.3V to REF + 0.3V
I
EAOUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA to 5mA
I
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2V to 0.2V
Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . 55°C to +150°C
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . +300°C
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
J, N, or D Packages
ORDER INFORMATION
The main gate drive output (OUT1) is controlled by the
pulse width modulator. The second output (OUT2) is in-
tended to activate an auxiliary switch during the off time
of the main switch, except that between each transition
there is deadtime where both switches are off, pro-
grammed by a single external resistor. This design offers
two options for OUT2, normal and inverted. In the -1 and
-2 versions, OUT2 is normal and can be used to drive
PMOS FETs. In the -3 and -4 versions, OUT2 is inverted
and can be used to drive NMOS FETs. In all versions,
both the main and auxiliary switches are held off prior to
startup and when the PWM command goes to zero duty
cycle. During fault conditions, OUT1 is held off while
OUT2 operates at maximum duty cycle with a guaran-
teed off time equal to the sum of the two deadtimes.
Undervoltage lockout monitors supply voltage (VDD), the
precision reference (REF), input line voltage (LINE), and
the shutdown comparator (SHTDWN).
these four have sensed a fault condition, recovery to full
operation is initiated with a soft start. VDD thresholds, on
and off, are 15V and 8.5V for the -2 and -4 versions, 9V
and 8.5V for the -1 and -3 versions.
If after any of
The UCC1580-x is specified for operation over the mili-
tary
temperature
range
of
UCC2580-x is specified from
UCC3580-x is specified from 0°C to 70°C. Package op-
tions include 16-pin surface mount and dual in-line.
55°C
40°C to 85°C. The
to
125°C.
The
DESCRIPTION (cont.)
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