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| 型號： | HOW |
| 英文描述： | How to check the Flash Version on M16C/62Application Note 99K/MAY.26.03 |
| 中文描述： | 如何檢查M16C/62Application注意99K/MAY.26.03的Flash版本 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 99K |
| 代理商： | HOW |
REB05B0002-0102Z
May 2003
Page 2 of
5
M16C/62 Group
How to check the Flash Version on M16C/62
3.0 Contents
3.1 The Flash identification register
The Flash identification register is a register not mentioned in the datasheet.
At M16C/62P series (0.2HND Flash technology) it is located at 01B4h.
At M16C/62A and M16C/62M series (0.5 DINOR Flash technology) it is located at 03B4h.
At M16C/62N series (0.35 HND Flash technology) it is also located at 03B4h.
A special procedure is needed to read out the correct value from this register.
Structure of the Flash identification register:
Flash identification register
Symbol
FIDR
Address
01B4H (M16C/62P series)
03B4h (M16C/62A, M16C62M, M16C/62N)
Read/Write
Bit
Symbol
Bit Name
Function
R
W
FIDR0
0
X
FIDR1
Flash identification value
Flash value output
b0 b1
DINOR: 1 1 (Note 1)
0.35 HND: 0 0
0.2 HND: 1 0
0
X
Nothing is assigned to these bits. In an attempt to write to these bits, please write
“0”. The value, if read, is indeterminate.
Note 1: This value is kept on the internal data bus latch. If external memory area or
SFR area is accessed during the readout procedure, the data may be changed.
Note 2: Although this register cannot be written, a special writing step is needed in order
to read out the correct value
0
X
3.2 Readout procedure
The readout procedure is shown in figure 1. This procedure is valid for any M16C/62 series, regardless of the
address of the Flash identification register. Before reading out the value of the Flash identification register
FIDR, ‘FFh’ must be written to it.
Please note, that the FIDR value is kept into the internal data bus latch. Therefore, if external memory
or SFR area is accessed between writing ‘FFh’ and reading out the value, the value that is read out,
may be changed.
Hence it is required to stop any access of external memory or SFR area between step 1 and step 2 and
between step 4 and step 5. Furthermore the interrupts and the DMA must be disabled.
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