SUB ADDRESS = 24H BIT NUMBER FUNCTION" />
參數(shù)資料
型號(hào)： HMP8156ACNZ
廠商： Intersil
文件頁(yè)數(shù)： 16/34頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO ENCODER NTSC/PAL 64MQFP
標(biāo)準(zhǔn)包裝： 84
類(lèi)型： NTSC/PAL 編碼器
應(yīng)用： 多媒體，視頻編輯
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-BQFP
供應(yīng)商設(shè)備封裝： 64-MQFP（14x14）
包裝： 托盤(pán)
23
FN4343.5
August 20, 2009
TABLE 27. START V_BLANK HIGH REGISTER
SUB ADDRESS = 24H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-1
Reserved
0000000B
0
Assert BLANK
Output Signal
(Vertical)
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
1B
TABLE 28. END V_BLANK REGISTER
SUB ADDRESS = 25H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
(Vertical)
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start inputting pixel
input data each noninterlaced input frame. The output video will be active starting on line
number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
13H
TABLE 29. FIELD CONTROL REGISTER 1
SUB ADDRESS = 26H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Field Detect
Window Size Low
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1X clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
80H
TABLE 30. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-4
Half Line Count
Reset Value
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
00000B
2
VSYNC Edge
Select
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = leading edge
1 = trailing edge
0B
1
FIELD Detect
Select
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = odd field
1 = even field
0B
0
Field Detect
Window Size High
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size
value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
0B
HMP8154, HMP8156A
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