參數(shù)資料
型號: HMD2M64B2-F10
廠商: Hanbit Electronics Co.,Ltd.
英文描述: Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V
中文描述: 同步DRAM模塊16Mbyte(2Mx64位),SO - DIMM插槽,4Banks,4K的參考。,3.3
文件頁數(shù): 6/10頁
文件大?。?/td> 87K
代理商: HMD2M64B2-F10
HANBit HSD2M64B2
URL:www.hbe.co.kr HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
I
CC2
NS
CKE
V
IH
(min)
CLK
V
IL
(max), t
CC
=
Input signals are stable
10
I
CC3
P
CKE
V
IL
(max), t
CC
=10ns
3
Active standby current in
power-down mode
I
CC3
PS
CKE&CLK
V
IL
(max)
t
CC
=
3
mA
I
CC3
N
CKE
V
IH
(min),
CS*
V
IH
(min), t
CC
=10ns
Input signals are changed
one time during 20ns
30
Active standby current in
non power-down mode
(One bank active)
I
CC3
NS
CKE
VIH(min)
CLK
VIL(max), t
CC
=
Input signals are stable
20
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
150
130
mA
2
Refresh current
I
CC5
t
RC
t
RC
(min)
160
150
mA
3
2
mA
Self refresh current
I
CC6
CKE
0.2V
450
mA
5
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V
±
0.3V, TA = 0 to 70
°
C)
PARAMETER
Value
UNIT
AC Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
Ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
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