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參數(shù)資料
| 型號： | HMD2M64B2-F10 |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V |
| 中文描述： | 同步DRAM模塊16Mbyte（2Mx64位），SO - DIMM插槽，4Banks，4K的參考。，3.3 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 87K |
| 代理商： | HMD2M64B2-F10 |
HANBit HSD2M64B2
URL:www.hbe.co.kr HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
/CE
Chip enable
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
/CAS
Column address
strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
/WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output
mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS
Power
supply/ground
Power and ground for the input buffers and the core logic.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
Voltage on Any Pin Relative to Vss
V
IN ,OUT
-1V to 4.6V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 4.6V
Power Dissipation
P
D
2W
Storage Temperature
T
STG
-55oC to 150oC
Short Circuit Output Current
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
I
OS
100mA
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HMD2M64B2-F8 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:Synchronous DRAM Module 16Mbyte (2Mx64-Bit), SO-DIMM, 4Banks, 4K Ref., 3.3V |
| HMD32M32M16EG | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:128Mbyte (32Mx32) 72-pin EDO Mode 4K Ref. SIMM Design 5V |
| HMD32M32M16EG-5 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:128Mbyte (32Mx32) 72-pin EDO Mode 4K Ref. SIMM Design 5V |
| HMD32M32M16EG-6 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:128Mbyte (32Mx32) 72-pin EDO Mode 4K Ref. SIMM Design 5V |
| HMD32M32M16G | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:128Mbyte (32Mx32) 72-pin Fast Page Mode 4K Ref. SIMM Design 5V |
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