參數(shù)資料
型號: HMD1M1Z1-6
廠商: Hanbit Electronics Co.,Ltd.
英文描述: 1Mbit(1Mx1bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design
中文描述: 為1Mbit(1Mx1bit)快速頁面模式,每1000刷新,20針郵編,5V的設計
文件頁數(shù): 4/6頁
文件大小: 188K
代理商: HMD1M1Z1-6
HANBit HMD1M1Z1
HANBit Electronics Co.,Ltd.
4
t
RCH
Read Command Hold Time to /CAS
0
0
ns
8
t
RRH
Read Command Hold Time to /RAS
0
0
ns
8
t
WCH
Write Command Hold Time
10
10
ns
t
WP
Write Command Pulse Width
10
10
ns
t
RWL
Write Command to /RAS Lead Time
15
15
ns
t
CWL
Write Command to /CAS Lead Time
13
15
ns
t
DS
Data-in Setup Time
0
0
ns
9
t
DH
Data-in Hold Time
10
10
ns
9
t
REF
Refresh Period (1024 Cycle)
16
16
ms
t
wcs
Write Command Setup Time
0
0
ms
7
t
CWD
/CAS to /WE delay time
15
15
ms
7,13
t
RWD
/RAS to /WE delay time
50
60
ns
7
t
AWD
Column Address to /WE delay time
25
30
ns
7
t
CPWD
/CAS precharge to /WE delay time
30
35
ns
7
t
CSR
/CAS Setup Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
15
t
CHR
/CAS Hold Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
16
t
RPC
/RAS Precharge to /CAS Hold Time
5
5
ns
t
CPA
Access Time from /CAS Precharge
30
35
ns
3
t
PC
Fast Page Mode Cycle Time
35
40
ns
t
CP
Fast Page Mode /RAS Precharge Time
10
10
ns
12
t
RASP
Fast Page Mode /CAS Pulse Time
50
200K
60
200K
ns
t
RHCP
/RAS Hold Time time from /CAS
Precharge
30
35
ns
t
RASS
/RAS Pulse Width(CBR self refresh)
100
100
us
t
PRS
/RAS Precharge Time(CBR self refresh)
90
110
ns
t
CHS
/CAS Hold Time(CBR self refresh)
-50
-50
ns
Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS refresh
cycles
before proper device operation is achieved.
2. Input voltage levels are V
IH
/
V
IL.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between
.
V
IH
and V
IL
are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
4. Operation with the
t
RCD
(max) limit insures that
t
RAC
(max) can be met,
t
RCD
(max) is specified as a reference point only,
if
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
<=
t
RCD
(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
OH
/
V
OL .
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