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參數(shù)資料
| 型號： | HMD16M72D9A-F10L |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | Synchronous DRAM Module 128Mbyte (8Mx72bit),DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V |
| 中文描述： | 同步DRAM模塊128Mbyte（8Mx72bit），帶ECC內(nèi)存的基礎(chǔ)上16Mx8，4Banks，4K的參考。，3.3 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 95K |
| 代理商： | HMD16M72D9A-F10L |
HANBit HSD16M72D9A
URL:www.hbe.co.kr
- 7 -
HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
CAS latency=3
2
Number of valid output data
CAS latency=2
-
1
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
-12
-10
-10L
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
CAS
latency=3
CAS
latency=2
CAS
latency=3
CAS
latency=2
CAS
latency=3
CAS
latency=2
7.5
8
10
10
CLK cycle time
t
CC
-
1000
-
1000
10
1000
12
1000
ns
1
5.4
6
6
6
CLK to valid
output delay
t
SAC
-
-
6
7
ns
1,2
2.7
3
3
3
Output data
hold time
t
OH
-
-
3
3
ns
2
CLK high pulse width
t
CH
2.5
3
3
3
ns
3
CLK low pulse width
t
CL
2.5
3
3
3
ns
3
Input setup time
t
SS
1.5
2
2
2
ns
3
Input hold time
t
SH
0.8
1
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
1
ns
3
CAS
latency=3
CAS
latency=2
5.4
6
6
6
ns
2
CLK to output
in Hi-Z
t
SHZ
-
-
6
7
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
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| HMD16M72D9A-F12 | Synchronous DRAM Module 128Mbyte (8Mx72bit),DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMD16M72D9A-F12 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:Synchronous DRAM Module 128Mbyte (8Mx72bit),DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V |
| HMD16M72D9A-F13 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:Synchronous DRAM Module 128Mbyte (8Mx72bit),DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V |
| HMD1M1Z1 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:1Mbit(1Mx1bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design |
| HMD1M1Z1-5 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:1Mbit(1Mx1bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design |
| HMD1M1Z1-6 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:1Mbit(1Mx1bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design |
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