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參數(shù)資料
| 型號(hào)： | HM66AEB9405BP-60 |
| 英文描述： | HM66AEB36105/HM66AEB18205 HM66AEB9405 Datasheet |
| 中文描述： | HM66AEB36105/HM66AEB18205 HM66AEB9405數(shù)據(jù)表 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 251K |
| 代理商： | HM66AEB9405BP-60 |
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HM66AEB36102/18202/9402
Rev.0.0, Dec. 2002, page 9 of 30
Burst Sequence
Linear Burst Sequence Table
(HM66AEB36102/18202)
SA0
SA0
External address
0
1
1st internal burst address
1
0
Truth Table
Operation
K
LD
R/
W
DQ
WRITE cycle
Load address, input write data on
consecutive K and
K
rising edges
L
→
H
L
L
Data in
Input
data
D
A
(A1)
D
A
(A2)
Input
clock
K(t+1)
↑
K
(t+1)
↑
READ cycle
Load address, read data on
consecutive C and
C
rising edges
L
→
H
L
H
Data out
Output
data
Q
A
(A1)
Q
A
(A2)
Output
clock
C
(t+1)
↑
C(t+2)
↑
NOP (No operation)
L
→
H
Stopped
H
×
×
High-Z
STANDBY (Clock stopped)
Notes: 1. H: high level, L: low level,
×
: don’t care,
↑
: rising edge.
2. Data inputs are registered at K and
K
rising edges. Data outputs are delivered at C and
C
rising
edges, except if C and
C
are high, then data outputs are delivered at K and
K
rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edges (low to
high) of K and are registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that (K) = /(
K
) = (C) = /(
C
) when clock is stopped. This is not essential, but
permits most rapid restart by overcoming transmission line charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal
burst address in accordance with the linear burst sequence.
×
Previous state
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM66AQB18202BP-40 | HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18202BP-50 | HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18202BP-60 | HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18202BP-75 | HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18204BP-30 | HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 Datasheet |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM66AQB18202BP-40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18202BP-50 | 功能描述:IC SRAM 36MBIT 200MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| HM66AQB18202BP-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18202BP-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AQB36102/HM66AQB18202 HM66AQB9402 Datasheet |
| HM66AQB18204BP-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 Datasheet |
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