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參數(shù)資料
| 型號： | HM5165805FLJ-5 |
| 元件分類： | DRAM |
| 英文描述： | 8M X 8 EDO DRAM, 50 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 34/35頁 |
| 文件大?。?/td> | 477K |
| 代理商： | HM5165805FLJ-5 |
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HM5164805F Series, HM5165805F Series
8
DC Characteristics (HM5164805F Series)
HM5164805F
-5
-6
Parameter
Symbol Min
Max
Min
Max
Unit
Test conditions
Operating current*
1, *2
I
CC1
—
115
—
105
mA
t
RC = min
Standby current
I
CC2
—
2
—
2
mA
TTL interface
RAS, CAS = V
IH
Dout = High-Z
—
0.5
—
0.5
mA
CMOS interface
RAS, CAS
≥ V
CC – 0.2 V
Dout = High-Z
Standby current
(L-version)
I
CC2
—
300
—
300
A
CMOS interface
RAS, CAS
≥ V
CC – 0.2 V
Dout = High-Z
RAS-only refresh current*
2
I
CC3
—
115
—
105
mA
t
RC = min
Standby current*
1
I
CC5
—5
—
5
mA
RAS = V
IH, CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
I
CC6
—
115
—
105
mA
t
RC = min
EDO page mode current*
1, *3
I
CC7
—
110
—
100
mA
RAS = V
IL , CAS cycle,
t
HPC = tHPC min
Battery backup current*
4
(Standby with CBR refresh)
(L-version)
I
CC10
—
1.2
—
1.2
mA
CMOS interface
Dout = High-Z
CBR refresh: t
RC = 15.6
s
t
RAS ≤ 0.3 s
Self refresh mode current
(L-version)
I
CC11
—
500
—
500
A
CMOS interface
RAS, CAS
≤ 0.2 V
Dout = High-Z
Input leakage current
I
LI
–5
5
–5
5
A
0 V
≤ Vin ≤ V
CC + 0.3 V
Output leakage current
I
LO
–5
5
–5
5
A
0 V
≤ Vout ≤ V
CC
Dout = disable
Output high voltage
V
OH
2.4
V
CC
2.4
V
CC
V
High Iout = –2 mA
Output low voltage
V
OL
0
0.4
0
0.4
V
Low Iout = 2 mA
Notes: 1. I
CC depends on output load condition when the device is selected.
I
CC max is specified at the
output open condition.
2. Address can be changed once or less while
RAS = V
IL.
3. Measured with one sequential address change per EDO cycle, t
HPC.
4. V
IH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
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