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參數(shù)資料
| 型號： | HM-6551883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 256 x 4 CMOS RAM |
| 中文描述： | 256 × 4 CMOS存儲(chǔ)器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 116K |
| 代理商： | HM-6551883 |
6-106
Timing Waveforms
The HM-6551/883 Read Cycle is initiated by the falling edge
of E. This signal latches the input address word and S2 into
on-chip registers providing the minimum setup and hold
times are met. After the required hold time, these inputs may
change state without affecting device operation. S2 acts as a
high order address and simplifies decoding. For the output to
be read, E, S1 must be low and W must be high. S2 must
have been latched low on the falling edge of E. The output
data will be valid at access time (TELQV). The HM-6551/883
has output data latches that are controlled by E. On the ris-
ing edge of E the present data is latched and remains in that
state until E falls. Also on the rising edge of E, S2 unlatches
and controls the outputs along with S1. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.
TELAX
(8) TAVEL
(10)
(8) TAVEL
A
NEXT
-1
TIME
0
1
2
3
4
5
REFERENCE
(9) TS2LEL
TELS2X
(11)
(9) TS2LEL
TELQV (1)
TAVQV (2)
TS1HQZ (5)
VALID OUTPUT
(3) TS1LQX
HIGH
D
Q
W
S1
S2
E
VALID
(19) TELEL
TELEH (6)
TEHEL (7)
(7) TEHEL
FIGURE 1. READ CYCLE
TRUTH TABLE
TIME
REFERENCE
INPUTS
OUTPUTS
FUNCTION
E
S1
S2
W
A
D
Q
-1
H
H
X
X
X
X
Z
Memory Disabled
0
X
L
H
V
X
Z
Addresses and S2 are Latched,
Cycle Begins
1
L
L
X
H
X
X
X
Output Enabled but Undefined
2
L
L
X
H
X
X
V
Data Output Valid
3
L
X
H
X
X
V
Outputs Latched, Valid Data,
S2 Unlatches
4
H
H
X
X
X
X
Z
Prepare for Next Cycle
(Same as -1)
5
X
L
H
V
X
Z
Cycle Ends, Next Cycle Begins
(Same as 0)
HM-6551/883
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM1-6551883 | 256 x 4 CMOS RAM |
| HM-65642 | RES,Metal Film,100KOhms,500WV,1+/-% Tol,-50,50ppm-TC |
| HM-65642883 | 8K x 8 Asynchronous CMOS Static RAM |
| HM1-65642883 | 8K x 8 Asynchronous CMOS Static RAM |
| HM1-65642B883 | 8K x 8 Asynchronous CMOS Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM-6551B883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256 x 4 CMOS RAM |
| HM-6561 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256 x 4 CMOS RAM |
| HM-6561/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256 x 4 CMOS RAM |
| HM-6561883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:256 x 4 CMOS RAM |
| HM-65642 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8K x 8 Asynchronous CMOS Static RAM |
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