參數(shù)資料
型號(hào)： HIP7010P
廠商： HARRIS SEMICONDUCTOR
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述： DATACOM, INTERFACE CIRCUIT, PDIP14
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 106K
代理商： HIP7010P
6
For enhanced noise immunity, the CLK input is a CMOS Schmitt
trigger input. See
Electrical Specifications
for input levels.
VPWOUT (Variable Pulse Width Out - Output),
VPWIN (Variable Pulse Width In - Input)
These two lines are used to interface to a J1850 bus trans-
ceiver, such as the Intersil HIP7020. VPWOUT is the vari-
able pulse width modulated output of the HIP7010’s symbol
encoder circuit. VPWIN is the inverted input to the symbol
decoder of the HIP7010. VPWIN is a Schmitt input.
SIN (Serial In - Input),
SOUT (Serial Out - Output),
SCK (Serial Clock - Output),
SACTIVE (Serial Bus Active - Output)
These four lines constitute the synchronous Serial Interface
(SERIAL)
interface of the HIP7010. See the
Serial Interface
(SERIAL) System
for details. SIN, SOUT, and SCK provide
the three principal connections to the Host controller. SIN is a
CMOS input. SOUT and SCK are three-state outputs which
are only activated during serial transfers. The SIN, SOUT, and
SCK pins contain integrated pull-down load devices which
provide termination on the bus whenever it is in a high imped-
ance state. The SACTIVE pin is a CMOS output, which pulls
low when the HIP7010 is communicating on the serial bus.
See
Serial Interface (SERIAL) System
and
Applications
Information
for more details.
RDY (Byte Ready - Input)
The Byte Ready (RDY) line is a “handshaking” input from the
Host. Each rising edge on the RDY pin signifies that the Host
has loaded a byte into its SERIAL transmit register and the
HIP7010 can retrieve it (by generating clocks on SCK) when
the HIP7010 is ready for the data. See
Serial Interface
(SERIAL) System
and
Applications Information
for more
details.
The RDY pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.
IDLE (Idle/Service Request - Output)
The IDLE output pin indicates that the J1850 Bus has been
in a passive state for at least
275
μ
s
and is now idle. If the
bus has been passive for a minimum of 239
μ
s and another
node initiates a new message, IDLE will pulse low for 1
μ
s.
In its role as a Service Request pin, a reset forces IDLE
high. Following the reset, IDLE remains high for 17 CLK
cycles and is then driven low. IDLE will remain low until 40
CLK cycles +1.5
μ
s after completion of the first Status/Con-
trol byte transfer. The IDLE pin will then resume its normal
role, remaining high until a
275
μ
s
lull (or 239
μ
s plus a pas-
sive to active transition) has been detected on the J1850
bus. This provides a handshake mechanism to ensure the
Host will reinitialize the HIP7010 each time the HIP7010 is
reset via POR, RESET, or Slow Clock Detect.
If IDLE is low when an echo failure causes the ERR bit to be
set in the Status byte, the IDLE pin will pulse high for 2
μ
s
and then return low (see Status/Control Register).
If IDLE is low when the host sets the NXT bit in the control
byte, the IDLE pin will pulse high for 2
μ
s and then return low
(see Status/Control Register).
In general a Status/Control byte transfer should be performed
each time IDLE goes low. See
Effects of Resets and Power-
Down
and
Applications Information
for more details.
The IDLE pin is an active low CMOS output. See
Operation
of the HIP7010
for more details.
STAT (Request Status/Control - Input)
The Request Status/Control (STAT) input pin is used by the
Host microcontroller to initiate an exchange of the Host’s con-
trol byte and the HIP7010’s status byte. A low to high transi-
tion on the STAT input signals the HIP7010 that the Host has
placed a control word in it’s SERIAL output register and is
ready to exchange it with the HIP7010’s status word. The
HIP7010 controls the exchange by generating the 8 SCKs
required. See
Serial Interface (SERIAL) System
and
Appli-
cations Information
for more details.
The STAT pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected.
RESET (Reset - Input)
The RESET input is a low level active input, which resets the
HIP7010. Resetting the HIP7010 forces SACTIVE high, dis-
ables the SOUT and SCK pins, forces the VPWOUT output
low, drives IDLE high, and returns the internal state machine
to its initial state. Following reset, the HIP7010 is inhibited
from transmitting or receiving J1850 messages until a Sta-
tus/Control Register transfer has been completed (see
Effects Of Resets And Power-Down
for more details).
The HIP7010 is also reset during initial power-on, by an
internal power-on-reset (POR) circuit.
Loss of a clock on the CLK input will cause a reset as
described previously under
CLK
.
If not used, the RESET pin should be tied to V
DD
.
For enhanced noise immunity, the
RESET
input is a CMOS
Schmitt trigger input. See
Electrical Specifications
for
input levels.
TEST (Test Mode - Input)
The TEST input provides a convenient method to test the
HIP7010 at the component level. Raising the TEST pin to a
high level causes the HIP7010 to enter a special TEST mode.
In the TEST mode, a special portion of the state machine is
activated which provides access to the Built-in-Test and diag-
nostic capabilities of the HIP7010 (see
Test Mode
for more
details).
The TEST pin contains an integrated pull-down load device
which will hold the pin low if it is left unconnected. In many
applications the TEST pin will be left unconnected, to allow
access via a board level ATE tester.
HIP7010
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP7010P WAF 制造商:Harris Corporation 功能描述:
HIP7020 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems
HIP7020 DIE 制造商:Harris Corporation 功能描述:
HIP7020AB 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems
HIP7020AP 制造商:Harris Corporation 功能描述:
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