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參數(shù)資料
| 型號： | HIP7010P |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDIP14 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 106K |
| 代理商： | HIP7010P |
11
SERIAL Bus Transfers
The HIP7010 is always configured as a SERIAL “master”. As
a master, the HIP7010 generates the transfer-synchronizing
clock on the SCK pin, transmits data on the SOUT pin, and
receives data on the SIN pin.
Whenever the HIP7010 receives a complete byte from the
J1850 bus via the VPWIN line, it automatically initiates an
unsolicitedSERIAL transfer. The unsolicited transfer trans-
mits the received (or reflected) byte to the Host and, if in the
midst of transmitting a message, retrieves the next byte from
the Host. While these unsolicited transfers are, strictly
speaking, asynchronous to the Host’s activities, there are
well defined rules which govern the minimum time between
unsolicited transfers (i.e., no two unsolicited transfers can
occur in less time than it takes to transfer one J1850 byte (8
x 64 = 512
μ
s). See
Applications Information
for more
details.
In addition to the unsolicited transfers which are based on
receipt of incoming J1850 messages, the Host can initiate
certain transfers in a more synchronous fashion. Handshak-
ingbetween the Host and the HIP7010 is provided by the
Byte Ready (RDY) and Request Status (STAT) pins. These
two pins are driven by the Host and trigger the HIP7010 to
initiate one of the two, unique, solicitedSERIAL transfers.
The Byte Ready (RDY) line is the first of two handshaking
inputs from the Host. Each rising edge on the RDY pin signi-
fies that the Host has loaded a byte into its serial transmit
register and the HIP7010 can retrieve it. If the J1850 bus is
available (i.e., IFS has elapsed) the rising edge of RDY is
interpreted as signalling the first byte of a new message. The
HIP7010 immediately performs a solicited SERIAL transfer
to load the first byte. Prior to performing the transfer, the
HIP7010 drives the J1850 bus high to initiate an SOF sym-
bol. The SOF is then followed by the eight symbols which
represent the transferred byte. If a J1850 message is
already in progress, the rising edge of RDY is interpreted as
signalling that the next byte of the message or of an IFR is
ready to be transferred from the Host. The HIP7010 will ini-
tiate the transfer, as an unsolicited transfer, when conditions
on the J1850 bus warrant the transfer (i.e., when the previ-
ously retrieved byte has been completely transmitted on the
J1850 bus or after EOD for an IFR).
While the rising edge of RDY is used to notify the HIP7010
that the Host is ready to supply the next byte, the level of
RDY following the actual serial transfer provides additional
information. Figure 1 depicts the use of RDY. By driving the
RDY line high and returning it low before the transfer has
been completed, the HIP7010 will detect a low. This is
referred to as a short RDY If the RDY line is brought high
and held high until the transfer is complete, a high level is
detected by the HIP7010. This is referred to as a long RDY
A short RDY signals a normal transfer, but a long RDY has
special significance. A long RDY indicates that the byte cur-
rently sitting within the Host is the last byte of a message or of
an IFR. When transmitting the body of a message or a Type 3
IFR the HIP7010 will automatically append the CRC after the
byte for which the long RDY was used. When responding with
a Type 1 or Type 2 IFR the response is a single byte, and as
such it is always the last byte. For sake of consistency the
HIP7010 requires a long RDY for Type 1 and Type 2 IFRs.
See
Status/Control Register
and
Application Information
for more details.
The other handshaking input is the Request Status/Control
(STAT) input pin. STAT is used by the Host microcontroller to
initiate an exchange of the Host’s control byteand the
HIP7010’s status byte A low to high transition on the STAT
input signals the HIP7010 that the Host has placed a control
word in it’s serial output register and is ready to exchange it
with the HIP7010’s status word. The HIP7010 will generate
the eight SCKs for the solicited transfer as soon as feasible.
To avoid confusion with the transfer of a received J1850
byte, STAT should generally be pulsed shortly after receiving
each data byte from the HIP7010. This technique is safe,
because once a J1850 message byte has been received
from or sent to the HIP7010, another unsolicited transfer is
guaranteed not to happen for at least 500
μ
s. A Control/Sta-
tus byte transfer should also be performed in response to
each high to low transition on the IDLE line. See
Applica-
tion Information
for more details.
Status/Control Register
The Status/Control Register is actually a pair of registers:
the Status Register and the Control Register. When the Host
initiates a Status/Control Register transfer by raising the
STAT input, the HIP7010 sends the contents of the Status
Register to the Host and simultaneously loads the Control
register with the byte received from the Host.
Status Register
The Status Register contains eight, read-only, status bits.
B7, EOD
When an EOD symbol has been received on
VPWIN and an IFR byte is received from the
J1850 bus, the End-of-Data flag (EOD) is set, dur-
ing the unsolicited transfer of the byte from the
HIP7010 to the Host. EOD remains set, until the
unsolicited transfer of the first byte of the next
frame.
EOD can be used to distinguish the IFR portion of
a frame from the message portion.
EOD is cleared by reset.
B6, MACK If MACK (Multi-byte ACKnowledge) is high, either
the MACK control bit has been set during a previ-
ous Status/Control Register transfer or a long nor-
malization bit has been received following an EOD.
When both MACK is set and the EOD flag (see B7,
EOD) is set, the most recent data byte transferred
is part of a Type 3 IFR.
The value of MACK is only relevant if EOD = 1.
MACK remains set until the unsolicited transfer of
the first byte of the next frame.
MACK is cleared by reset.
7
6
5
0
4
3
2
1
0
EOD
MACK
FTU
4X
CRC
ERR
BRK
HIP7010
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