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參數(shù)資料
| 型號： | HIP6008 |
| 廠商： | Intersil Corporation |
| 英文描述： | Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor |
| 中文描述： | 降壓脈寬調(diào)制（PWM）控制器和輸出電壓監(jiān)視器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 209K |
| 代理商： | HIP6008 |
7
Figure 6 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
IN
and C
O
each represent numerous physical capacitors.
Locate the HIP6008 within 3 inches of the MOSFET, Q1.
The circuit traces for the MOSFET’s gate and source
connections from the HIP6008 must be sized to handle up to
1A peak current.
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
SS
close to the SS pin because the internal current source is
only 10
μ
A. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
+
-
BAND GAP
REFERENCE
1.26V
VID0
VID1
VID2
VID3
FB
COMP
DACOUT
ERROR
AMPLIFIER
21.5k
1.7k
10.7k
5.4k
2.7k
2.9k
DAC
+
-
FIGURE 5. DAC FUNCTION SCHEMATIC
L
O
CO
UGATE
PHASE
Q1
D2
V
IN
V
OUT
RETURN
HIP6008
C
IN
L
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
+12V
HIP6008
SS
GND
V
CC
BOOT
D1
L
O
CO
V
OUT
L
Q1
D2
PHASE
+V
IN
C
BOOT
C
VCC
C
SS
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
V
OUT
OSC
REFERENCE
LO
CO
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6008
Z
IN
COMPARATOR
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
FIGURE 8. VOLTAGE - MODE BUCK CONVERTER COMPEN-
SATION DESIGN
HIP6008
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