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參數(shù)資料
| 型號(hào)： | HIP4082IP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 功率晶體管 |
| 英文描述： | 30000 SYSTEM GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 1.3 A FULL BRDG BASED MOSFET DRIVER, PDIP16 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 72K |
| 代理商： | HIP4082IP |
5
HIP4082
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
1
BHB
B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin.
2
BHI
B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides
BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V
DD
). An internal
100
μ
A pull-up to V
DD
will hold BHI high, so no connection is required if high-side and low-side outputs are to
be controlled by the low-side input.
3
BLI
B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not con-
nected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V
to 15V (no greater than V
DD
). An internal 100
μ
A pull-up to V
DD
will hold BLI high if this pin is not driven.
4
ALI
A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not con-
nected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL
(Pin 5). DIS (Pin 8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V
to 15V (no greater than V
DD
). An internal 100
μ
A pull-up to V
DD
will hold ALI high if this pin is not driven.
5
DEL
Turn-on DELay. Connect resistor from this pin to V
SS
to set timing current that defines the dead time between
drivers. All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by de-
laying the turn-on of all drivers. The voltage across the DEL resistor is approximately Vdd -2V.
6
V
SS
Chip negative supply, generally will be ground.
7
AHI
A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI
high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides
AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V
DD
). An internal
100
μ
A pull-up to V
DD
will hold AHI high, so no connection is required if high-side and low-side outputs are to
be controlled by the low-side input.
8
DIS
DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other in-
puts. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal
levels of 0V to 15V (no greater than V
DD
). An internal 100
μ
A pull-up to V
DD
will hold DIS high if this pin is not
driven.
9
AHB
A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-
strap diode and positive side of bootstrap capacitor to this pin.
10
AHO
A High-side Output. Connect to gate of A High-side power MOSFET.
11
AHS
A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
12
V
DD
Positive supply to control logic and lower gate drivers. De-couple this pin to V
SS
(Pin 6).
13
ALO
A Low-side Output. Connect to gate of A Low-side power MOSFET.
14
BLO
B Low-side Output. Connect to gate of B Low-side power MOSFET.
15
BHS
B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
16
BHO
B High-side Output. Connect to gate of B High-side power MOSFET.
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| HIP4082IPR4485 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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