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參數(shù)資料
| 型號： | HIP1012CB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 512 MACROCELL 3.3 VOLT ZERO POWER ISP CP - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封裝： | PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 173K |
| 代理商： | HIP1012CB |
9
Exploring and Using the HIP1012EVAL1
Board
(Figure 13)
The HIP1012EVAL1 is a flexible platform for a thorough
evaluation of the HIP1012 dual power supply controller. This
eval board comes in three separate parts allowing the
evaluation of two principal configurations. To simulate a
passive back plane implementation both the GENERIC and
LOAD sections are first connected together and then the
GENERIC board is connected onto the BUS board. For an
active backplane or for the HIP1012 on an interposer board
configuration, the BUS and GENERIC sections are first
connected together and then the load board is connected
onto the GENERIC board.
The HIP1012EVAL1 board has many built in features
besides the configuration flexibility described above.
The BUS board is designed so that adding suitable
connectors and/or power supply capacitive filtering is very
easy to do through the numerous through holes for each rail
voltage and ground. Passive backplane power sequencing
can be simulated by simply shortening the finger lengths for
the rail(s) that need to come up after initial ground
connection is made.
The GENERIC board, is a flexible evaluation platform with
many designed in features for user customizing and
evaluation. The circuit is shipped default configured in the
3.3V and 5V controller mode by jumpers for easy
reconfiguration (see Table 3 for jumper settings). The default
configuration is highlighted in Table 3. The default OC levels
are 5A on the 3.3V and 1A on the 5V supplies. To operate
the HIP1012 GENERIC board in its default configuration (3V
and 5V) a dedicated +12V power supply must be provided
for the HIP1012 through tie point, W1 on the generic board.
To operate the board in the +12V and 5V mode, JP2 and
JP3 need to be reconfigured (see Table 3) and a suitable
current load needs to be provided. A programmable
electronic current load is an excellent evaluation tool for this
device. The load board is configured to sink about 3
±
1A at
3.3V. For 12V operation, the load must be modified to sink
less than 5A, otherwise, an OC failure upon power will occur.
The GENERIC board is provided with a single pair of
RF1K49156 N-Channel MOSFETs, if currents > 6A are to be
evaluated then an additional pair of RF1K49156 MOSFETs
can be installed in the provided space. Additionally for even
higher current evaluations space for TO-252AA, DPAK or
D
2
PAK devices has been provided. Contact Intersil
Semiconductor for availability of Power MOSFET samples.
Tie points on the output side of the GENERIC board are
provided for direct access to a high current load.
Performance customizing can easily be accomplished by
substitution/addition of several SMD components to the
existing layout or by utilizing the included bread board area.
See Table 5 for the component listing and applicable
formulae.
The LOAD board, consists of four load switches, output
resistive and capacitive loads and output on indicating
LED’s. The resistive loads are configured so that either no
current, a low or high current load relative to the OC trip
point can be invoked for both supplies. An OC event can be
emulated by switching both switches of any one output to the
on position (see Table 4, OC conditions highlighted). Load
connection sequencing can be done by shorting the desired
finger lengths. As noted, the GENERIC board is default
configured for 3V and 5V operation. For 12V evaluation
replace RL3 and RL4 with a suitable load.
TABLE 3. JUMPER CONFIGURATION
JP #
OPEN /
SHORT
CIRCUIT CONDITION
1
Short to
GND
2-3
PWRON2 shorted to ground. True HOT
SWAP mode. PWRON1 only controls reset
with rising edge.
1
Short to 5V
1-2
PWRON2 shorted to 5V. Reset and turn on
controlled only by PWRON1. Single input
control mode
1
Open
PWRON2 will be internally pulled high to
~2.5V, compatible with logic signal. The
HIP1012 can not turn on until PWRON2 is
driven low.
2
Open
HIP1012 must be powered from a
dedicated +12V power supply.
2
Short
HIP1012 V
DD
pin connected to same 12V
supply as load. See Decoupling Concerns in
Critical Items section.
3
Open
C1 in circuit. Charge pump capacitor
necessaryfor5Vand12Voperatingmodeto
develop ~ 11.7V for 12VG voltage.
3
Short
Shorts across charge pump capacitor,
C1. Capacitor not needed in 3V and 5V
mode.
4
Short to
GND
1-2
HIP1012 MODE/PWRON1 shorted to
ground. True HOT SWAP mode. PWRON2
rising edge only resets HIP1012.
4
Short to 5V
2-4
MODE/PWRON1 shorted to 5V. PWRON2
only single mode control.
4
Short to
V
DD
2-3
HIP1012 MODE/PWRON1 connected to
V
DD
pin. This along with JP3 installed
invokes and configures HIP1012 for 3V
and 5V operation. Controlled by PWRON2
4
Open
HIP1012 MODE/PWRON1 will be internally
pulled high to ~2.5V, compatible with logic.
Redundant controller mode when each
PWRON pin is driven by separate signals.
TABLE 4. LOAD CURRENT
SW13
SW14
3.3V
I
OUT
A
0
SW11
SW12
5.0V
I
OUT
A
0
0
0
0
0
0
1
2
0
1
0.5
1
0
4
1
0
0.74
1
1
6
1
1
1.24
HIP1012, HIP1012A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP1012CB-T | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual Power Distribution Controller |
| HIP1012EVAL1 | 功能描述:電源管理IC開發(fā)工具 GENERIC EVAL BRD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| HIP1012EVAL2 | 功能描述:電源管理IC開發(fā)工具 RAID EVALUATION BRD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| HIP1013 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Cost Dual Power Distribution Controller |
| HIP1013_04 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Cost Dual Power Distribution Controller |
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