13
HIP1012 Evaluation Circuit for Disk Drive Hot Swap
HIP1012EVAL2
Introduction
The HIP1012EVAL2 is specifically designed to test and
demonstrate hot swapping of disk drives onto passive 12V
and 5V power buses using the HIP1012 Hot-Swap control
IC. The small size of the board allows it to be included in a
shuttle alongside the disk drive during evaluation. The
outlined area on the board represents the actual area used
for PCB implementation.
Description
The HIP1012EVAL2 board is provided with a standard Molex
four-terminal disk-drive power connector. The solder holes
J2 allows the board to be connected to a power supply
connector on the disk-drive shuttle. PGOOD, PWRON1,
PWRON2, 5VG. 12VG, CTIM, V
DD
and GND are all
accessible through a ribbon cable.
With JP1 installed, the HIP1012 is powered from the same
12V power supply as the disk drive motor. JP2 connects the
control signal PWRON2 to ground allowing the unit to be
plugged directly into the power bus for automatic, controlled
start up. In this configuration, PWRON1 is available to reset
the HIP1012 in case of an over-current trip. Otherwise the
HIP1012 can be reset by toggling the voltage on V
DD
. With
JP2 removed, the circuit is controlled using one or both of
the PWRON signal lines. The HIP1012EVAL2 is shipped
with both jumpers installed.
The HIP1012EVAl2 is configured with a 10k
RILIM
resistor (R
5
) setting the nominal current limit threshold to
100mV. The 12V current sense resistor (R
2
) is 20m
and
the 5V current sense resistor (R
1
) is 100m
.
These values
set the nominal current limits to 5A and 1A respectively.
The C
TIM
capacitor (C
2
) sets the time out period to
approximately 9ms.
Control Connections, Fault Notification,
and Test Points
HIP1012 EVAL2 is shipped with JP2 installed so that a
connected disk drive is started simply by connecting 12V
and 5V power supplies to J2. In this configuration, the
ribbon cable is not necessary, since the HIP1012 can be
reset by toggling the voltage on V
DD
. This configuration
represents a disk drive that would be removed after any
over-current trip and would start immediately upon
insertion. Additional control is available using the ribbon
cable and resetting the HIP1012 by applying a rising edge
to PWRON1. If redundant control is desired, removing JP2
makes the second control signal PWRON2 available to
start or reset the chip. An example of this control
configuration would be to turn the chip on using PWRON1
and reset it using PWRON2. The PGOOD pin is an open
drain logic output which can be tied high through a resistor
for fault indication. Upon detection of either over-current or
under-voltage fault conditions, PGOOD goes low and
remains low until the fault condition is cleared.
Also included on the ribbon cable are additional monitor
points for 12VG, 5VG and C
TIM
. These are included for
monitoring during evaluation and they are not necessary for
operation.
Data Line Considerations
The HIP1012 does not integrate data bus line switches,
although control of the data bus can be assisted by the time-
out feature of the HIP1012. During the time-out period, the
operating system software can determine whether to halt I/O
activity to a disk drive which is undergoing an under-voltage
or over-current fault as indicated by the status of PGOOD.
HIP1012, HIP1012A