參數(shù)資料
| 型號： | HI7191IP |
| 廠商： | Intersil |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-PDIP |
| 標準包裝： | 18 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
7
FN4138.8
June 1, 2006
Load Test Circuit
Pin Descriptions
20 LEAD
DIP, SOIC
PIN NAME
DESCRIPTION
1
SCLK
Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the
falling edge.
2
SDO
Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
3
SDIO
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
4CS
Chip Select Input. Used to select the HI7191 for a serial data transfer cycle. This line can be tied to DGND.
5
DRDY
An Active Low Interrupt indicating that a new data word is available for reading.
6
DGND
Digital Supply Ground.
7AVSS
Negative Analog Power Supply (-5V).
8VRLO
External Reference Input. Should be negative referenced to VRHI.
9VRHI
External Reference Input. Should be positive referenced to VRLO.
10
VCM
Common Mode Input. Should be set to halfway between AVDD and AVSS.
11
VINLO
Analog Input LO. Negative input of the PGIA.
12
VINHI
Analog Input HI. Positive input of the PGIA. The VINHI input is connected to a current source that can be used to check the
condition of an external transducer. This current source is controlled via the Control Register.
13
AVDD
Positive Analog Power Supply (+5V).
14
AGND
Analog Supply Ground.
15
DVDD
Positive Digital Supply (+5V).
16
OSC2
Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise.
17
OSC1
Oscillator Clock Input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the device,
or an external oscillator can drive OSC1. The oscillator frequency should be 10MHz (Typ).
18
RESET
Active Low Reset Pin. Used to initialize the HI7191 registers, filter and state machines.
19
SYNC
Active Low Sync Input. Used to control the synchronization of a number of HI7191s. A logic ‘0’ initializes the converter.
20
MODE
Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking
(Mode = 0) for the Serial Port.
ESD Test Circuits
FIGURE 5A.
FIGURE 5B.
FIGURE 5.
V1
R1
CL (INCLUDES STRAY
DUT
CAPACITANCE)
FIGURE 4.
DUT
HUMAN BODY
CESD = 100pF
MACHINE MODEL
CESD = 200pF
R1
CESD
R1 = 10MΩ
R2
R2 = 1.5kΩ
R2 = 0Ω
±
V
CHARGED DEVICE MODEL
R1
R1 = 1GΩ
R2
R2 = 1Ω
±
V
DUT
DIELECTRIC
HI7191
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