參數資料
| 型號： | HI7191IB |
| 廠商： | Intersil |
| 文件頁數： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-SOIC |
| 標準包裝： | 38 |
| 位數： | 24 |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個差分，單極；1 個差分，雙極 |
17
FN4138.8
June 1, 2006
Programming the Serial Interface
It is useful to think of the HI7191 interface in terms of
communication cycles. Each communication cycle happens
in 2 phases. The first phase of every communication cycle
is the writing of an instruction byte. The second phase is
the data transfer as described by the instruction byte. It is
important to note that phase 2 of the communication cycle
can be a single byte or a multi-byte transfer of data. For
example, the 3-byte Data Output Register can be read
using one multi-byte communication cycle rather than three
single-byte communication cycles. It is up to the user to
maintain synchronism with respect to data transfers. If the
system processor “gets lost” the only way to recover is to
reset the HI7191. Figure 13 shows both a 2-wire and a
3-wire data transfer.
Several formats are available for reading from and writing to
the HI7191 registers in both the 2-wire and 3-wire protocols.
A portion of these formats is controlled by the CR<2:1> (BD
and MSB) bits which control the byte direction and bit order
of a data transfer respectively. These two bits can be written
in any combination but only the two most useful will be
discussed here.
The first combination is to reset both the BD and MSB bits
(BD = 0, MSB = 0). This sets up the interface for descending
byte order and MSB first format. When this combination is
used the user should always write the Instruction Register
such that the starting byte is the most significant byte
address. For example, read three bytes of DR starting with
the most significant byte. The first byte read will be the most
significant in MSB to LSB format. The next byte will be the
next least significant (recall descending byte order) again in
MSB to LSB order. The last byte will be the next lesser
significant byte in MSB to LSB order. The entire word was
read MSB to LSB format.
The second combination is to set both the BD and MSB bits
to 1. This sets up the interface for ascending byte order and
LSB first format. When this combination is used the user
should always write the Instruction Register such that the
starting byte is the least significant byte address. For
example, read three bytes of DR starting with the least
significant byte. The first byte read will be the least
significant in LSB to MSB format. The next byte will be the
next greater significant (recall ascending byte order) again in
LSB to MSB order. The last byte will be the next greater
significant byte in LSB to MSB order. The entire word was
read MSB to LSB format.
After completion of each communication cycle, The HI7191
interface enters a standby mode while waiting to receive a
new instruction byte.
Instruction Byte Phase
The instruction byte phase initiates a data transfer
sequence. The processor writes an 8-bit byte (Instruction
Byte) to the Instruction Register. The instruction byte informs
the HI7191 about the Data transfer phase activities and
includes the following information:
Read or Write cycle
Number of Bytes to be transferred
Which register and starting byte to be accessed
Data Transfer Phase
In the data transfer phase, data transfer takes place as set
by the Instruction Register contents. See Write Operation
and Read Operation sections for detailed descriptions.
OSC1
CS
SCLK
29
33
37
41
45
89
121
125
FIGURE 12. SCLK OUTPUT IN SELF-CLOCKING MODE
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
DATA TRANSFER
CYCLE
CS
SDIO
FIGURE 13A. 2-WIRE, 3-BYTE READ OR WRITE TRANSFER
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
DATA TRANSFER
CYCLE
CS
SDIO
SDO
FIGURE 13B. 3-WIRE, 3-BYTE READ TRANSFER
HI7191
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| HI7191IBZ | 功能描述:模數轉換器 - ADC ADC 24BIT SIGMADELTA 20 IND RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI7191IBZ-T | 功能描述:模數轉換器 - ADC ADC 24BIT SIGMADELTA 20 IND RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI7191IP | 功能描述:IC ADC 24BIT PROGBL SER 20-PDIP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| HI7191IPZ | 功能描述:模數轉換器 - ADC W/ANNEAL ADC 24BIT SIGMADELTA 20PDIP RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI73127 | 制造商:Hanna 功能描述:Bulk |
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