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參數(shù)資料
| 型號： | HI7191IB |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-SOIC |
| 標準包裝： | 38 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
21
FN4138.8
June 1, 2006
G2 through G0 - Bits 7 through 5 select the gain of the
input analog signal. The gain is accomplished through a
programmable gain instrumentation amplifier that gains up
incoming signals from 1 to 8. This is achieved by using a
switched capacitor voltage multiplier network preceding the
modulator. The higher gains (i.e., 16 to 128) are achieved
through a combination of a PGIA gain of 8 and a digital
multiply after the digital filter (see Table 7). The gain will
affect noise and Signal to Noise Ratio of the conversion.
These bits are cleared to a gain of 1 (G2, G1, G0 = 000) after
a RESET is applied to the part.
BO - Bit 4 is the Transducer Burn-Out Current source
enable bit. When this bit is set (BO = 1) the burn-out current
source connected to VINHI internally is enabled. This current
source can be used to detect the presence of an external
connection to VINHI. This bit is cleared after a RESET is
applied to the part.
SB - Bit 3 is the Standby Mode enable bit used to put the
HI7191 in a lower power/standby mode. When this bit is set
(SB = 1) the filter nodes are halted, the DRDY line is set high
and the modulator clock is disabled. When this bit is cleared
the HI7191 begins operation as described by the contents of
the Control Register. For example, if the Control Register is
programmed for Self Calibration Mode and a notch
frequency to 10Hz, the HI7191 will perform the self
calibration before providing the data at the 10Hz rate. This
bit is cleared after a RESET is applied to the part.
BD - Bit 2 is the Byte Direction bit used to select the multi-
byte access ordering. The bit determines the either
ascending or descending order access for the multi-byte
registers. When set (BD = 1) the user can access multi-byte
registers in ascending byte order and when cleared (BD = 0)
the multi-byte registers are accessed in descending byte
order. This bit is cleared after a RESET is applied to the part.
MSB - Bit 1 is used to select whether a serial data transfer
is MSB or LSB first. This bit allows the user to change the
order that data can be transmitted or received by the
HI7191. When this bit is cleared (MSB = 0) the MSB is the
first bit in a serial data transfer. If set (MSB = 1), the LSB is
the first bit transferred in the serial data stream. This bit is
cleared after a RESET is applied to the part.
SDL - Bit 0 is the Serial Data Line control bit. This bit selects
the transfer protocol of the serial interface. When this bit is
cleared (SDL = 0), both read and write data transfers are
done using the SDIO line. When set (SDL = 1), write
transfers are done on the SDIO line and read transfers are
done on the SDO line. This bit is cleared after a RESET is
applied to the part.
Reading the Data Output Register
The HI7191 generates an active low interrupt (DRDY)
indicating valid conversion results are available for reading. At
this time the Data Output Register contains the latest
conversion result available from the HI7191. Data integrity is
maintained at the serial output port but it is possible to miss a
conversion result if the Data Output Register is not read within a
given period of time. Maintaining data integrity means that if a
Data Output Register read of conversion N is begun but not
finished before the next conversion (conversion N + 1) is
complete, the DRDY line remains active low and the data being
read is not overwritten.
In addition to the Data Output Register, the HI7191 has a one
conversion result storage buffer. No conversion results will be
lost if the following constraints are met.
1) A Data Output Register read cycle is started for a given
conversion (conversion X) 1/fN - (128*1/fOSC) after DRDY
initially goes active low. Failure to start the read cycle may
result in conversion X + 1 data overwriting conversion X results.
For example, with fOSC = 10MHz, fN = 2kHz, the read cycle
must start within 1/2000 - 128(1/106) = 487
μs after DRDY went
low.
2) The Data Output Register read cycle for conversion X must
be completed within 2(1/fN)-1440(1/fOSC) after DRDY initially
goes active low. If the read cycle for conversion X is not
complete within this time the results of conversion X + 1 are lost
and results from conversion X + 2 are now stored in the data
output word buffer.
Completing the Data Output Register read cycle inactivates the
DRDY interrupt. If the one word data output buffer is full when
this read is complete this data will be immediately transferred to
the Data Output Register and a new DRDY interrupt will be
issued after the minimum DRDY pulse high time is met.
Writing the Control Register
If data is written to byte 2 and/or byte 1 of the Control Register
the DRDY output is taken high and the device re-calibrates if
written to a calibration mode. This action is taken because it is
assumed that by writing byte 2 or byte 1 that the user either
reprogrammed the filter or changed modes of the part.
However, if a single data byte is written to byte 0, it is assumed
that the gain has NOT been changed. It is up to the user to re-
calibrate the HI7191 after the gain has been changed by this
method. It is recommended that the entire Control Register be
written to when changing the selected gain. This ensures that
the part is re-calibrated before the DRDY signal goes low
indicating valid data is available.
TABLE 7. GAIN SELECT BITS
G2
G1
G0
GAIN
GAIN ACHIEVED
0
1
PGIA = 1, Filter Multiply = 1
0
1
2
PGIA = 2, Filter Multiply = 1
0
1
0
4
PGIA = 4, Filter Multiply = 1
0
1
8
PGIA = 8, Filter Multiply = 1
1
0
16
PGIA = 8, Filter Multiply = 2
1
0
1
32
PGIA = 8, Filter Multiply = 4
1
0
64
PGIA = 8, Filter Multiply = 8
1
128
PGIA = 8, Filter Multiply = 16
HI7191
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