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參數(shù)資料
| 型號： | HI5662/6IN |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADC DUAL 8-BIT 60MSPS 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 60M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 功率耗散（最大）： | 670mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，雙極 |
3-11
Detailed Description
Theory of Operation
The HI5662 is a dual 8-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 14
depicts the circuit for the front end differential-in-differential-
out sample-and-hold (S/H) ampliers. The switches are
controlled by an internal sampling clock which is a non-
overlapping two phase signal,
φ1 and φ2, derived from the
master sampling clock. During the sampling phase,
φ1, the
input signal is applied to the sampling capacitors, CS. At the
same time the holding capacitors, CH, are discharged to
analog ground. At the falling edge of
φ1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase,
φ2, the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-
and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the I/QIN pins see only the on-resistance of
a switch and CS. The relatively small values of these
components result in a typical full power input bandwidth of
250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, identical pipeline subconverter stages,
each containing a two-bit ash converter and a two-bit
multiplying digital-to-analog converter, follow the S/H circuit
with the last stage being a two bit ash converter. Each
converter stage in the pipeline will be sampling in one phase
and amplifying in the other clock phase. Each individual
subconverter clock signal is offset by 180 degrees from the
previous stage clock signal resulting in alternate stages in
the pipeline performing the same operation.
The output of each of the identical two-bit subconverter
stages is a two-bit digital word containing a supplementary
bit to be used by the digital error correction logic. The output
of each subconverter stage is input to a digital delay line
which is controlled by the internal sampling clock. The
function of the digital delay line is to time align the digital
outputs of the identical two-bit subconverter stages with the
corresponding output of the last stage ash converter before
applying the results to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the nal
eight bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specied as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VREFOUT
The HI5662 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. VROUT must be connected to VRIN when using the
internal reference voltage.
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL INPUT
VOLTAGE
(I/QIN+ - I/QIN-)
OFFSET BINARY OUTPUT CODE
MSB
LSB
I/QD7
I/QD6
I/QD5
I/QD4
I/QD3
I/QD2
I/QD1
I/QD0
+Full Scale (+FS) -7/16LSB
0.498291V
11111111
+FS
- 17/16LSB
0.494385V
11111110
+9/16LSB
2.19727mV
10000000
-7/16LSB
-1.70898mV
01111111
-FS + 19/16LSB
-0.493896V
00000001
-Full Scale (-FS) + 9/16LSB
-0.497803V
00000000
NOTE:
8. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.
-
+
-
CH
CS
CH
I/QIN+
VOUT+
VOUT-
I/QIN-
Φ1
Φ2
Φ1
FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD
HI5662
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5662EVAL2 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 HI5662 EVAL PL ATFORM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5662IN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
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| HI5667/6CA | 制造商:Rochester Electronics LLC 功能描述:A/D, 8-BIT,60MSPS,COM TEMP,28 SSOP,TTL/CMOS (HI5767/6, 10- - Bulk |
| HI5667/6CB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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