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參數(shù)資料
| 型號： | HI5628INZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 125MSPS DUAL 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 330mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 125M |
10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
39-32
QD7 (MSB) Through
QD0 (LSB)
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.
1-5, 48-46
ID7 (MSB) Through
ID0 (LSB)
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
8
SLEEP
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20
A active pulldown current.
15
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable.
23
REFIO
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1
F cap to ground when internal reference is enabled.
22
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x IFSADJ.
14, 24
ICOMP1, QCOMP1
Reduces noise. Connect each to AVDDwith 0.1F capacitor. The ICOMP1 and QCOMP1 pins MUST be
tied together externally.
13, 18, 19, 25
AGND
Analog Ground Connections.
17
IOUTB
The complementary current output of the I channel. Bits set to all 0s gives full scale current.
16
IOUTA
Current output of the I channel. Bits set to all 1s gives full scale current.
20
QOUTB
The complementary current output of the Q channel. Bits set to all 0s gives full scale current.
21
QOUTA
Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27
NC
No Connect. Recommended: Connect to ground.
12, 26
AVDD
Analog Supply (+2.7V to +5.5V).
6, 7, 10, 28, 30,
31, 41, 44
DGND
Digital Ground.
9, 29, 40, 45
DVDD
Supply voltage for digital circuitry (+2.7V to +5.5V).
43
ICLK
Clock input for I channel. Positive edge of clock latches data.
42
QCLK
Clock input for Q channel. Positive edge of clock latches data.
HI5628
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5630 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| HI5630/8CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5630/8CN WAF | 制造商:Harris Corporation 功能描述: |
| HI5630_03 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| HI5630CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
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