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參數(shù)資料
| 型號(hào)： | HI3338KIBZ |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT CMOS 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 50M |
| 產(chǎn)品目錄頁(yè)面： | 1236 (CN2011-ZH PDF) |
8
Applications
The output of the HI3338 can be resistively divided to match
a doubly terminated 50
or 75 line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter's output impedance. Figure 5
shows such an application. Note that because of the HCT
input structure, the HI3338 could be operated up to +7.5V
VDD and VREF+ supplies and still accept 0V to 5V CMOS
input voltages.
If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical
application, with the output capable of driving
±2V into
multiple 50
terminated lines.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended
handling practices for CMOS devices are described in
AN6525. “Guide to Better Handling and Operation of CMOS
Integrated Circuits.”
OPERATING
OPERATING VOLTAGE
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.
INPUT SIGNALS
To prevent damage to the input protection circuit, input
signals should never be greater than VDD nor less than VSS.
Input currents must not exceed 20mA even when the power
supply is off.
UNUSED INPUTS
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VCC or
GND, whichever is appropriate.
NOTES:
1. Both VREF+ pin and 392 resistor should be bypassed within
1/
4 inch.
2. Keep nodal capacitance at CA3450 pin 3 as low as possible.
3. VOUT Range = ±3V at CA3450.
CLOCK
8 DATA
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
VDD
COMP
VSS
HI3338
VOUT
VREF+
VEE
12
13
11
10
R
VREF-
R
11
UP TO 5 OUTPUT LINES
FOR R = 75
, 3 LINES
FOR R = 50
VOUT1
VOUTN
+3.00V AT 25mA
4.7
F
TAN
4.7
F TAN
4.7
F
TAN
0.1
F
CER.
0.1
F
CER.
0.1
F CER.
14
+6V
-6V
392
392
1%
10k
1k
3
4, 5, 12, 13
R
+
VOUT = ± 1.5VPEAK
6
7, 8
9
+
-
CA3450
ADJUST
OFFSET
5pF
BITS
1%
4.7
F
TAN
0.1
F
CER.
FIGURE 6. HI3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
HI3338
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI3338KIP | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, CMOS R2R D/A Converter |
| HI33815 | 制造商:HARRIS 功能描述:* |
| HI3-381-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPST Analog Switch |
| HI3-384-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DPST Analog Switch |
| HI3-387-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPDT Analog Switch |
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