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參數(shù)資料
| 型號： | HI-8482D |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | ARINC 429 DUAL LINE RECEIVER |
| 中文描述： | DUAL LINE RECEIVER, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 676K |
| 代理商： | HI-8482D |
PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
ARINC inputs - IN1A, IN1B, IN2A, IN2B
V(A) - V(B)
V(A) - V(B)
V(A) - V(B)
(|V(A)| - |V(B)|) / 2
Input resistance - input A to input B
Input resistance - input A or B to Gnd
Input capacitance - input A to B
Input capacitance - input A or B to Gnd
VIH
VIL
VNULL
VCM
RI
RG
CI
CG
OUTA = 1
OUTB = 1
OUTA = OUTB = 0
Frequency = 80KHz
Supply pins floating
Supply pins floating
Filter caps disconnected - see note 1
Filter caps disconnected - see note 1
6.5
-6.5
-2.5
10
-10
0
±5
50K
25K
5
5
13
-13
2.5
volts
volts
volts
volts
ohms
ohms
pF
pF
30K
19K
10
10
Tes t inputs - TESTA, TESTB
Logic 1 input voltage
Logic 0 input voltage
Logic 1 input current (magnitude)
Logic 0 input current
VIH
VIL
IIH
IIL
ARINC inputs to Gnd
ARINC inputs to Gnd
VIH = 2.7V
VIL = 0V
2.7
volts
volts
μA
μA
0.8
15
1
5
0.5
Outputs - OUT1A, OUT1B, OUT2A, OUT2B
Voltage - sourcing 100μA
Voltage - sourcing 2.8mA
Voltage - sinking 100μA
Voltage - sinking 2.0mA
Rise time
Fall time
Propagation delay - low to high (ARINC)
Propagation delay - high to low (ARINC)
Propagation delay - low to high (TESTA/B)
Propagation delay - low to high (TESTA/B)
VOH
VOH
VOL
VOL
tr
tf
tPLH
tPHL
tTLH
tTHL
TA = 25°C
Full temperature range
TA = 25°C
Full temperature range
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C and filter caps disconnected
CL = 50pF, TA = 25°C and filter caps disconnected
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C
4
3.5
volts
volts
volts
volts
ns
ns
ns
ns
ns
ns
0.08
0.8
70
70
40
30
600
600
50
50
Supply current
+VS current
+VS current
-VS current
-VS current
+VL current
+VL current
IDD
IDD
IEE
IEE
ICC
ICC
±VS = ±15V, TA =25°C, TESTA and TESTB = 0V
±VS = ±12V, TA =25°C, TESTA and TESTB = 0V
±VS = ±15V, TA =25°C, TESTA and TESTB = 0V
±VS = ±12V, TA =25°C, TESTA and TESTB = 0V
±VS = ±15V, TA =25°C, TESTA and TESTB = 0V
±VS = ±12V, TA =25°C, TESTA and TESTB = 0V
3.7
3
8.7
7.4
9
8.6
7
6
15
14
20
18
mA
mA
mA
mA
mA
mA
HI-8482
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Voltage at ARINC Inputs:.......................................................-29V to +29V
Voltage at Any Other Input:.............................................-0.3V to V + 0.3V
Output Short Circuit Protected: .............................................Not Protected
Storage Temperature Range: .........................................-65°C to +150°C
Soldering Temperature: (Ceramic).................................30 sec. at +300°C
(Plastic - leads)........................10 sec. at +280°C
(Plastic - body) ................................+220°C Max.
L
Supply Voltage, +V :......................................................................+20 VDC
-V : .......................................................................-20 VDC
+V :........................................................................+7 VDC
L
Operating Temperature Range: (Industrial).........................-40°C to +85°C
(Hi-Temp) ........................-55°C to +125°C
(Military) ..........................-55°C to +125°C
Internal Power Dissipation: ..............................................................900mW
(Voltages referenced to Gnd = 0V)
Notes:
1. Guaranteed by design.
±12
V
±15, V = +5V, Operating temperature range (unless otherwise noted)
<
<
S
HOLT INTEGRATED CIRCUITS
5
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PDF描述 |
|---|---|
| HI-8482DT | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8482J | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8482PSI | ARINC 429 DUAL LINE RECEIVER |
| HI-8482PST | ARINC 429 DUAL LINE RECEIVER |
| HI-8482S | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8482DT | 制造商:Holt Integrated Circuits 功能描述:Line Receiver 2RX 20-Pin CDIP |
| HI8482J | 制造商:Holt Integrated Circuits 功能描述:Line Receiver 2RX 20-Pin PLCC |
| HI-8482J | 制造商:Holt Integrated Circuits 功能描述:Line Receiver 2RX 20-Pin PLCC |
| HI-8482JF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 DUAL LINE RECEIVER |
| HI-8482JI | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 DUAL LINE RECEIVER |
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