參數(shù)資料
型號: HI-8282CM-03
廠商: HOLT INTEGRATED CIRCUITS INC
元件分類: 微控制器/微處理器
英文描述: ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
中文描述: 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, CDIP40
封裝: ROHS COMPLIANT, SIDE BRAZED, CERAMIC, DIP-40
文件頁數(shù): 6/14頁
文件大?。?/td> 448K
代理商: HI-8282CM-03
REPEATEROPERATION
The repeater mode of operation allows a data word that has been
received by the HI-8282 to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into the receiver
shiftregister,the
flagwillgolow. Alogic"0"isplacedontheSEL
line and
is strobed. This is the same procedure as for normal
receiver operation and it places the lower byte (16) of the data word
on
the
data
bus.
By
strobing
at
the
same
D/R
EN
PL1
HI-8282
time as
SEL is then taken high and
byte of the data word on the data bus. By strobing
time as
, the second byte will also be placed into the FIFO. The
data word is now ready to be transmitted according to the parity
programmedintothecontrolwordregister.
, the byte will also be placed into the transmitter FIFO.
is strobed again to place the upper
EN
at the same
Innormaloperation,eitherbyteofareceiveddatawordmayberead
from the receiver latches first by use of SEL input. During repeater
operation however, the lower byte of the data word must be read
first. This is necessary because, as the data is being read, it is also
being loaded into the FIFO and the transmitter FIFO is always
loadedwiththelowerbyteofthedatawordfirst.
EN
PL2
EN
429DO
429DO
ARINC BIT
NULL
DATA
DATA
DATA
NULL
NULL
WORD GAP
BIT 1
NEXT WORD
BIT 32
BIT 31
BIT 30
CWHLD
t
CWSET
t
CWSTR
t
DATA BUS
CWSTR
VALID
DATA BUS
SELEN
t
D/R
t
ENSEL
t
DATAEN
t
D/REN
t
END/R
t
EN
t
ENSEL
t
SELEN
t
DATAEN
t
ENDATA
t
ENDATA
t
ENEN
t
BYTE 1 VALID
BYTE 2 VALID
HOLT INTEGRATED CIRCUITS
4-34
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相關代理商/技術參數(shù)
參數(shù)描述
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