參數(shù)資料
型號(hào): HFCT-5218M
英文描述: 622 Mb/s Single Mode Laser Transceiver for ATM, SONET OC-12/SDH STM-4 (L4.1)(應(yīng)用于ATM, SONET OC-12/SDH STM-4 (L4.1)的622 Mb/s單模式激光收發(fā)器)
中文描述: 622 Mb / s的對(duì)ATM,SONET的OC-12/SDH的STM - 4(L4.1)(應(yīng)用于自動(dòng)取款機(jī),SONET的OC-12/SDH的STM - 4(L4.1)的622桶/單模激光收發(fā)器擰單模式激光收發(fā)器)
文件頁數(shù): 4/16頁
文件大小: 493K
代理商: HFCT-5218M
4
mount components be used. Use
tantalum capacitors for the 10 μF
capacitors and mono-lithic,
ceramic bypass capacitors for the
0.1 μF capacitors. Also, it is
recommended that a surface-
mount coil inductor of 1 μH be
used. Ferrite beads can be used
to replace the coil inductors
when using quieter V
CC
supplies,
but a coil inductor is recom-
mended over a ferrite bead to
provide low frequency noise
filtering as well. Coils with a low,
series dc resistance (<0.7 ohms)
and high, self-resonating
frequency are recommended. All
power supply components need
to be placed physically next to
the V
CC
pins of the receiver and
transmitter. Use a good, uniform
ground plane with a minimum
number of holes to provide a low-
inductance ground current return
path for the signal and power
supply currents.
Although the front mounting
posts make contact with the
metallized housing these posts
should not be relied upon to
provide adequate electrical
connection to the plated housing.
It is recommended to either
connect these front posts to
chassis ground or allow them to
remain unconnected. These front
posts should not be connected to
signal ground.
Figure 4 shows the recommended
board layout pattern.
In addition to these
recommendations, Agilent’s
Application Engineering staff is
available for consulting on best
layout practices with various
vendors serialiser/deserialiser,
clock generator.
20.32
(0.800)
TOP VIEW
2 x 1.9 ± 0.1
(0.075 ± 0.004
20.32
(0.800)
2.54
(0.100)
9 x 0.8 ± 0.1
(0.032 ± 0.004
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Figure 4. Recommended Board Layout Pattern
Figure 5. 622.08 Mb/s OC-12 ATM-SONET/SDH Reference Design Board
Reference Design
Agilent has developed a reference
design for multimode and single-
mode OC-12 ATM-SONET/SDH
applications shown in Figure 5.
This reference design uses a
Vitesse Semiconductor Inc.’s
VSC8117 clock recovery/clock
generation/serializer/deserializer
integrated circuit and a PMC-
Sierra Inc. PM5355 framer IC.
Application Note 1178 documents
the design, layout, testing and
performance of this reference
design. Gerber files, schematic
and application note are available
from the Agilent Fiber-Optics
Components’ web site at the URL
of
http://semiconductor.agilent.
com/fiber.
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