參數(shù)資料
型號： HFA3860AIV96
廠商： INTERSIL CORP
元件分類： 無繩電話/電話
英文描述： Circular Connector; No. of Contacts:5; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-5 RoHS Compliant: No
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
封裝： 7 X 7 X 1 MM, PLASTIC, TQFP-48
文件頁數(shù)： 9/39頁
文件大?。?/td> 251K
代理商： HFA3860AIV96
2-139
I/Q A/D Interface
The PRISM baseband processor chip (HFA3860A) includes
two 3-bit Analog to Digital converters (A/Ds) that sample the
analog input from the IF down converter. The I/Q A/D clock,
samples at twice the chip rate. The nominal sampling rate is
22MHz.
The interface specifications for the I and Q A/Ds are listed in
Table 2.
The voltages applied to pin 16, V
REFP
and pin 17, V
REFN
set the references for the internal I and Q A/D converters. In
addition, V
REFP
is also used to set the RSSI A/D converter
reference. For a nominal I/Q input of 500mV
P-P
, the
suggested V
REFP
voltage is 1.75V, and the suggested
V
REFN
is 0.86V. V
REFN
should never be less than 0.25V.
Figure 6 illustrates the suggested interface configuration for
the A/Ds and the reference circuits.
Since these A/Ds are intended to sample AC voltages, their
inputs are biased internally and they should be capacitively
coupled. The HPF corner frequency in the baseband receive
path should be less than 1kHz.
.
The A/D section includes a compensation (calibration) circuit
that automatically adjusts for temperature and component
variations of the RF and IF strips. The variations in gain of
limiters, AGC circuits, filters etc. can be compensated for up
to
±
4dB. Without the compensation circuit, the A/Ds could
see a loss of up to 1.5 bits of the 3 bits of quantization. The
A/D calibration circuit adjusts the A/D reference voltages to
maintain optimum quantization of the IF input over this
variation range. It works on the principle of setting the
reference to insure that the signal is at full scale (saturation)
a certain percentage of the time. Note that this is not an
AGC and it will compensate only for slow variations in signal
levels (several seconds).
The procedure for setting the A/D references to
accommodate various input signal voltage levels is to set the
reference voltages so that the A/D calibration circuit is
operating at half scale with the nominal input. This leaves
the maximum amount of adjustment room for circuit
tolerances.
RXCLK
RX_PE
MD_RDY
RXD
PROCESSING
PREAMBLE/HEADER
LSB
DATA PACKET
MSB
NOTE:
MD_RDY active after CRC16. See detailed timing diagrams (see Figures 22, 23, 24).
FIGURE 5. RX PORT TIMING
HEADER
FIELDS
DATA
TABLE 2. I, Q, A/D SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
Full Scale Input Voltage (V
P-P
)
0.25
0.50
1.0
Input Bandwidth (-0.5dB)
-
20MHz
-
Input Capacitance (pF)
-
5
-
Input Impedance (DC)
5k
-
-
FS (Sampling Frequency)
-
22MHz
-
0.15
μ
F
0.15
μ
F
3.9K
8.2K
9.1K
I
Q
2V
I
IN
Q
IN
V
REFP
V
REFN
HFA3860A
0.01
μ
F
0.01
μ
F
FIGURE 6. INTERFACES
HFA3860A
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