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CONFIGURATION REGISTER 11 ADDRESS (2Ch) SQ2 ACQ THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0-7) of the carrier phase variance threshold used for acquisition.
CONFIGURATION REGISTER 12 ADDRESS (30h) SQ1 CCA THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for CCA
estimation. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal
quality measurement made during acquisition on CCA antenna dwell. A lower value on this threshold will increase the
probability of detection and the probability of false alarm. Set the threshold according to instructions in the text.
CONFIGURATION REGISTER 13 ADDRESS (34h) SQ1 CCA THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for CCA. This
register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurement made during acquisition on CCA antenna dwell.
CONFIGURATION REGISTER 14 ADDRESS (38h) ED OR RSSI THRESHOLD
Bit 7:6
R/W, But Not Used Internally
Bits 5:0
This register contains the value for the RSSI threshold for measuring and generating energy detect (ED). When the RSSI
exceeds the threshold ED is declared. ED indicates the presence of energy in the channel.
To disable the ED signal so that it has no affect on the CCA logic, the threshold must be set to a 3Fh (all ones).
MSB
LSB
Bits (0:5)
5 4 3 2 1 0
0 0 0 0 0 0
00h (Min)
RSSI_STAT
1 1 1 1 1 1
3Fh (Max)
CONFIGURATION REGISTER 15 ADDRESS (3Ch) SFD TIMER
Bits 7:0
This register is programmed with an 8-bit value which represents the length of time for the demodulator to search for a SFD
in a receive Header. Each bit increment represents 1 symbol period. Failure to find the SFD will result in a return to
acquisition mode.
CONFIGURATION REGISTER 16 ADDRESS (40h) SIGNAL FIELD DBPSK
Bits 7:0
This register contains an 8-bit value defining the data packet modulation as DBPSK. This value will be a 0Ah for 802.11, and
is used in the transmitted Signalling Field of the header. This value will also be used for detecting the modulation type on the
received Header.
CONFIGURATION REGISTER 17 ADDRESS (44h) SIGNAL FIELD DQPSK
Bits 7:0
This register contains the 8-bit value defining the data packet modulation as DQPSK. This value will be a 14h for full protocol
operation at a data rate of 2MBPS and is used in the transmitted Signalling Field of the header. This value will also be used
for detecting the modulation type on the received header.
CONFIGURATION REGISTER 18 ADDRESS (48h) SIGNAL FIELD BMBOK
Bits 7:0
This register contains the 8-bit value defining the data packet modulation as BMBOK. This value will be a 37h for operation
at a data rate of 5.5MBPS and is used in the transmitted Signalling Field of the header. This value will also be used for
detecting the modulation type on the received header.
CONFIGURATION REGISTER 19 ADDRESS (4Ch) SIGNAL FIELD QMBOK
Bits 7:0
This register contains the 8-bit value defining the data packet modulation as QMBOK. This value will be a 6Eh for operation
at a data rate of 11MBPS and is used in the transmitted Signalling Field of the header. This value will also be used for
detecting the modulation type on the received header.
HFA3860A