參數(shù)資料
型號(hào)： HFA1113IB
廠商： HARRIS SEMICONDUCTOR
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Hook-Up Wire; Conductor Size AWG:30; No. Strands x Strand Size:Solid; Jacket Color:Purple; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
中文描述： BUFFER AMPLIFIER, PDSO8
文件頁(yè)數(shù)： 9/22頁(yè)
文件大?。?/td> 568K
代理商： HFA1113IB
197
HFA1113/883
D
j
x 45
o
D3
B
h x 45
o
A
A1
E
L
L3
e
B3
L1
D2
D1
e
1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010
E H
S
S
0.010
E F
S
S
-E-
0.007
E F
M
S
H S
B1
-H-
-F-
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD LEADLESS CERAMIC CHIP CARRIER
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.060
0.100
1.52
2.54
6, 7
A1
0.050
0.088
1.27
2.23
-
B
-
-
-
-
-
B1
0.022
0.028
0.56
0.71
2, 4
B2
0.072 REF
1.83 REF
-
B3
0.006
0.022
0.15
0.56
-
D
0.342
0.358
8.69
9.09
-
D1
0.200 BSC
5.08 BSC
-
D2
0.100 BSC
2.54 BSC
-
D3
-
0.358
-
9.09
2
E
0.342
0.358
8.69
9.09
-
E1
0.200 BSC
5.08 BSC
-
E2
0.100 BSC
2.54 BSC
-
E3
-
0.358
-
9.09
2
e
0.050 BSC
1.27 BSC
-
e1
0.015
-
0.38
-
2
h
0.040 REF
1.02 REF
5
j
0.020 REF
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.91
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
5
5
3
NE
5
5
3
N
20
20
3
Rev. 0 4/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
10. Materials: Compliant to MIL-I-38535.
Ceramic Leadless Chip Carrier Packages (CLCC)
Spec Number
511106-883
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