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參數(shù)資料
| 型號(hào)： | HEF40195B |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit universal shift register(4位通用移位寄存器(MSI)) |
| 中文描述： | 4位通用移位寄存器（4位通用移位寄存器（微星）） |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 77K |
| 代理商： | HEF40195B |
J
7
P
P
4
H
M
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V
DD
V
TYPICAL FORMULA FOR P (
μ
W)
Dynamic power
dissipation per
package (P)
5
1900 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
8300 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
22 800 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
10
15
Fig.4
Waveforms showing set-up times, hold times for J, K and P
n
inputs; minimum MR pulse width, MR to output delays and MR to CP
recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be specified
as negative values.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HEF4020B | 14-stage binary counter(14級(jí)二進(jìn)制計(jì)數(shù)器(MSI)) |
| HEF4024B | 7-stage binary counter(7級(jí)二進(jìn)制計(jì)數(shù)器(MSI)) |
| HEF4040B | 12-stage binary counter(12級(jí)二進(jìn)制計(jì)數(shù)器) |
| HEF4041B | Quadruple true/complement buffer |
| HEF4041BD | Quadruple true/complement buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF40195BD | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BF | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BN | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BP | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BT | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:4-bit universal shift register |
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