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參數(shù)資料
| 型號： | HEF40195B |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 4-bit universal shift register(4位通用移位寄存器(MSI)) |
| 中文描述： | 4位通用移位寄存器（4位通用移位寄存器（微星）） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 77K |
| 代理商： | HEF40195B |
January 1995
2
Philips Semiconductors
Product specification
4-bit universal shift register
HEF40195B
MSI
DESCRIPTION
The HEF40195B is a fully synchronous edge-triggered
4-bit shift register with a clock input (CP), four synchronous
parallel data inputs (P
0
to P
3
), two synchronous serial data
inputs (J, K), a synchronous parallel enable input (PE),
buffered parallel outputs from all 4-bit positions (O
0
to O
3
),
a buffered inverted output from the last bit position (O
3
)
and an overriding asynchronous master reset input (MR).
Each register stage is of a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is
edge-triggered on the LOW to HIGH transition of the CP
input. When PE is LOW, data are loaded into the register
from P
0
to P
3
on the LOW to HIGH transition of CP. When
PE is HIGH, data are shifted into the first register position
from J and K and all the data in the register are shifted one
position to the right on the LOW to HIGH transition of CP.
D-type entry is obtained by interconnecting J and K.
When J is HIGH and K is LOW, the first stage is in the
toggle mode. When J is LOW andK is HIGH, the first stage
is in the hold mode.
A LOW on MR resets all four bit positions (O
0
to
O
3
= LOW, O
3
= HIGH) independent of all other input
conditions.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
HEF40195BP(N):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
HEF40195BD(F):
HEF40195BT(D):
( ): Package Designator North America
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HEF4020B | 14-stage binary counter(14級二進制計數(shù)器(MSI)) |
| HEF4024B | 7-stage binary counter(7級二進制計數(shù)器(MSI)) |
| HEF4040B | 12-stage binary counter(12級二進制計數(shù)器) |
| HEF4041B | Quadruple true/complement buffer |
| HEF4041BD | Quadruple true/complement buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HEF40195BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BF | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit universal shift register |
| HEF40195BT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:4-bit universal shift register |
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