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14.
Timer1
KING BILLION ELECTRONICS CO., LTD
駿
億
電
子
股
份
有
限
公
司
HE84G761B
HE80004 Series
April 25, 2005
This specification is subject to change without notice. Please contact sales person for the latest version before use.
36
V0.92
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.
The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode.
And it comes from the fast clock “FCK” at fast clock only mode.
Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of
T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero
when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately
and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be
set before enabling Timer1.
T1H
T1L
< Timer1 Counter >
Decreases 1
Count To
0xFFFFh
The contents of
T1H and T1L are
almost loaded into
Timer1 immediately
when Timer1 is
enabled after reset.
Auto reload
when Timer1
is underflow
Yes
No
Timer1
Interrupt
Request
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
Description
IER
0x02
TC1_IER
2
R/W
0: TC1 interrupt is disabled. (default)
1: TC1 interrupt is enabled.
Low byte of TC1 pre-load value
High byte of TC1 pre-load value
0: TC1 is disabled. (default)
1: TC1 is enabled.
T1L
T1H
0x03
0x04
T1L[7:0]
T1H[7:0]
7~0
7~0
W
W
OP1
0x09
TC1E
2
R/W