參數(shù)資料
型號(hào)： HE84G752B
廠商： King Billion Electronics Co., Ltd.
英文描述： 8-BIT MICRO-CONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 40/49頁(yè)
文件大?。?/td> 474K
代理商： HE84G752B
The following table shows the related interrupt sources, user can read the ID[2:0] to retrieve what is the
current highest priority of pending interrupts. The ID[2:0] bits will be cleared when user read the related
registers. For example, when an interrupt happened and the content of ID[2:0] is “101”, this means that
LRS error and THR empty happen; user can read the LSR register to clear the ID[2] bit and ID[0] bit can
also be cleared by reading the IEIR or writing data into THR register.
KING BILLION ELECTRONICS CO., LTD
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HE84G752B
HE80004 Series
January 21, 2005
This specification is subject to change without notice. Please contact sales person for the latest version before use.
40
V0.93
Level
None
Highest
Second
IEIR Bit [2:0]
0 0 0
1 0 0
0 1 0
Source of Interrupt
Interrupt Reset Control
None
Reading LSR register to clear ID[2]
Reading RBR register to clear ID[1]
Reading IEIR register or Writing
THR register to clear ID[0]
None
LSR error flags (OE/PE/FE/BI)
LSR receiver data ready flag (DR)
Third
0 0 1
LSR flag THR Empty (THRE)
19.4.
Line Control Register
The line control register allows user to configure the asynchronous data transfer format and set the UART
function. Reading from the register is allowed to check the current settings of the communication.
Bit 7
BRGE
Bit 6
SB
Bit 5
SP
Bit 4
EPS
Bit 3
PEN
Bit 2
STB
Bit 1
WLS1
Bit 0
WLS0
Name
Description
WLS[1..0]
Word Length Select
“00”: word length = 5
“01”: word length = 6
“10”: word length = 7
“11”: word length = 8
Stop Bit Length
‘0’: Stop bit length = 1
‘1’: Stop bit length = 1.5 when WLS[1..0]=”00”
‘1’ Stop bit length = 2 when WLS[1..0]=”01”,”10”,”11”
Parity Selection
“xx0”: No Parity
“001”: odd Parity
“011”: even Parity
“101”: Stick Parity 1
“111”: Stick parity 0
Set Break
When enable the break control bit causes a break condition to be transmitted (SOUT is
forced to a logic 0 state). This condition exists until disabled by resetting this bit to
logic 0.
‘0’: disable break; ‘1’: enable break
Baud Rate Generator
‘0’: disable baud rate clock generator
‘1’: enable baud rate clock generator
STB
[SP, EPS, PEN]
SB
BRGE
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