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21.4.
Line Control Register
KING BILLION ELECTRONICS CO., LTD
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HE84760B
HE80004 Series
June 29, 2005
This specification is subject to change without notice. Please contact sales person for the latest version before use.
41
V1.0
The line control register allows user to configure the asynchronous data transfer format and set the UART
function. Reading from the register is allowed to check the current settings of the communication.
Bit 7
BRGE
Bit 6
SB
Bit 5
SP
Bit 4
EPS
Bit 3
PEN
Bit 2
STB
Bit 1
WLS1
Bit 0
WLS0
Name
Description
WLS[1..0]
Word Length Select
“00”: word length = 5
“01”: word length = 6
“10”: word length = 7
“11”: word length = 8
Stop Bit Length
‘0’: Stop bit length = 1
‘1’: Stop bit length = 1.5 when WLS[1..0]=”00”, else Stop bit length = 2
Parity Selection
“xx0”: No Parity
“001”: odd Parity
“011”: even Parity
“101”: Stick Parity 1
“111”: Stick parity 0
Set Break
When enable the break control bit causes a break condition to be transmitted (SOUT is
forced to a logic 0 state). This condition exists until disabled by resetting this bit to
logic 0.
‘0’: disable break; ‘1’: enable break
Baud Rate Generator
‘0’: disable baud rate clock generator
‘1’: enable baud rate clock generator
STB
[SP, EPS, PEN]
SB
BRGE