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參數(shù)資料
| 型號： | HDMP-1034 |
| 英文描述： | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| 中文描述： | 1.4 GBd接收芯片組與CIMT編碼器/解碼器和可變數(shù)據(jù)速率（帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd接收器） |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HDMP-1034 |
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Line Code Description
The HDMP-1032/1034 line code
is Conditional Invert Master Tran-
sition (CIMT) as illustrated in
Figure 9. The CIMT line code
uses three types of words: Data
words, Control words, and Idle
words. Idle words are generated
internally by the Tx when both
TXDATA and TXCNTL are low.
Each word consists of a Word
Field (W-Field) followed by a
Coding Field (C-Field). The
C-Field has a master transition.
Users can send arbitrary informa-
tion carried by Data or Control
Words. The DC balance of the
line code is enforced automati-
cally by the Tx. Idle words have
a single rising edge at the master
transition when operating in
non-enhanced simplex mode.
The coding definitions are sum-
marized in the table on the next
page. Note that the leftmost bit in
each table is the first bit to be
transmitted in time, while the
rightmost bit is the last bit to
be transmitted.
Data Word Codes
In Data Word mode, all 16 bits
of the Tx are transmitted to
the Rx, along with a flag bit. If
TXFLGENB=1, then the user
controls this bit with TXFLAG;
otherwise it is internally set to
alternate.
Control Word Codes
In Control Word mode, 14 bits are
transmitted to the Rx. The lower
7 bits X0-X6 are sent in the
w0-w6 space, and the upper
7 bits X7-X13 are sent in the
w9-w15 space. Bits w7 and w8
are forced 01 for true, and 10
for inverted control words. The
shifting of the word field is for
backward compatibility with pre-
vious versions of G-Links chip sets.
Idle Word and Error Codes
Two Idle Words, IW1a and IW1b
are provided. Unused word codes
are mapped into Error States.
Enhanced Simplex Mode
In this mode (ESMPXENB=1),
the flag bit is scrambled at the
Tx and descrambled at the Rx.
Since the Rx uses the scrambled
flag bit for frame alignment, it is
also defined for Control and Idle
Words. However, the flag bit is
only available to the user in the
Data Word mode. The first bit
w0 is also scrambled to aid word
alignment.
Figure 9. HDMP-1032/1034 (Tx/Rx Pair) Line Code.
Appendix: Internal Architecture Information
WORD
FIELD
16 BITS
CODING
FIELD
4 BITS
IDLE
WORD
SERIAL
BIT
STREAM
WORD K
WORD K+1
MASTER
TRANSITION
MASTER
TRANSITION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP-1514 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
| HDMP1526 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| HDMP-1526 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
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