參數(shù)資料
型號(hào): HDJD-J822-SCR00
英文描述: Agilent HDJD-J822-SCR00 Color Management System Feedback Controller
中文描述: 安捷倫HDJD - J822 - SCR00色彩管理系統(tǒng)反饋控制器
文件頁(yè)數(shù): 11/18頁(yè)
文件大小: 118K
代理商: HDJD-J822-SCR00
11
Notes on Sampling Frequency and
PWM Output Frequency
The sampling frequency, f
SAMP
,
which is the frequency at which
HDJD-J822 samples the tricolor
photosensor, is related to the
system clock frequency, f
CLK
.
The output PWM frequency,
f
PWM
, is also related to f
CLK
. The
system clock is sourced from
either the internal oscillator or
an external clock.
Calculation example:
f
CLK
= 2.5 MHz (nominal)
f
SAMP
= f
CLK
/25087 = 100 Hz
(nominal)
f
PWM
= f
CLK
/4095 = 610 Hz
(nominal)
The internal oscillator frequency
varies from part-to-part but it
will not vary significantly during
operation.
Register Description
The user controls and configures
HDJD-J822 by programming a
set of internal registers, through
the I2C protocol. Refer to
Application Note 5070
for
programming guide and register
description.
Figure 2. START/STOP condition.
S
P
START CONDITION
STOP CONDITION
SDA
SCL
I
2
C Interface
Description
The programming interface to
HDJD-J822 is a standard 2-wire
serial bus, which follows the I
2
C
data transmission protocol. This
protocol defines a
transmitter
as a device that sends data to
the bus and a
receiver
as a
device that receives data from
the bus.
A
master
is a device that
initiates a data transfer on the
bus, generates the clock signal
and terminates the data
transfer. A device addressed by
the master is called a
slave
. Both
master and slave can act as a
transmitter or a receiver but the
master controls the direction for
data transfer.
The bus consists of a serial clock
(SCL) and a serial data (SDA)
line. Both lines are bi-directional
and connected to the positive
power supply through a pull-up
resistor. When the bus is free,
both lines are HIGH.
HDJD-J822’s I
2
C bus interface
always
operates as a slave
transceiver in standard mode.
Standard mode has a data
transfer rate of up to 100 kbit/s.
START/STOP Condition
To begin an I
2
C data transfer,
the master must send a unique
signal to the bus called a
START
condition. This is defined as a
HIGH to LOW transition on the
SDA line while SCL is HIGH.
The master terminates the
transfer by sending another
unique signal to the bus called a
STOP
condition. This is defined
as a LOW to HIGH transition on
the SDA line while SCL is HIGH.
The bus is considered to be busy
after a START (S) condition. It
will be considered free a certain
time after the STOP (P)
condition. The bus stays busy if
a repeated START (Sr) is sent
instead of a STOP condition.
The START and repeated START
conditions are functionally
identical.
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